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[TableGen] Add a backend to generate MacroFusion predicators
`FusionPredicate` is used to predicate if target instruction matches the requirement. The targets can be firstMI, secondMI or both. The `Fusion` contains a list of `FusionPredicate`. The generated code will be like: ``` bool isNAME(const TargetInstrInfo &TII, const TargetSubtargetInfo &STI, const MachineInstr *FirstMI, const MachineInstr &SecondMI) { auto &MRI = SecondMI.getMF()->getRegInfo(); /* Predicates */ return true; } ``` A boilerplate class called `SimpleFusion` is added. `SimpleFusion` has a predefined structure of predicates and accepts predicate for `firstMI`, predicate for `secondMI` and epilog/prolog as arguments. The generated code for `SimpleFusion` will be like: ``` bool isNAME(const TargetInstrInfo &TII, const TargetSubtargetInfo &STI, const MachineInstr *FirstMI, const MachineInstr &SecondMI) { auto &MRI = SecondMI.getMF()->getRegInfo(); /* Prolog */ /* Predicate for `SecondMI` */ /* Wildcard */ /* Predicate for `FirstMI` */ /* Check One Use */ /* Tie registers */ /* Epilog */ return true; } ```
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‎llvm/include/llvm/Target/TargetInstrPredicate.td

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@@ -95,6 +95,12 @@ class MCOperandPredicate<int Index> : MCInstPredicate {
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// Return true if machine operand at position `Index` is a register operand.
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class CheckIsRegOperand<int Index> : MCOperandPredicate<Index>;
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// Return true if machine operand at position `Index` is a virtual register operand.
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class CheckIsVRegOperand<int Index> : MCOperandPredicate<Index>;
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// Return true if machine operand at position `Index` is not a virtual register operand.
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class CheckIsNotVRegOperand<int Index> : CheckNot<CheckIsVRegOperand<Index>>;
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// Return true if machine operand at position `Index` is an immediate operand.
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class CheckIsImmOperand<int Index> : MCOperandPredicate<Index>;
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‎llvm/include/llvm/Target/TargetSchedule.td

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@@ -584,3 +584,116 @@ class MemoryQueue<ProcResourceKind PR> {
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class LoadQueue<ProcResourceKind LDQueue> : MemoryQueue<LDQueue>;
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class StoreQueue<ProcResourceKind STQueue> : MemoryQueue<STQueue>;
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// The target instruction that FusionPredicate will be evaluated on.
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class FusionTarget;
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def first : FusionTarget;
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def second : FusionTarget;
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def both : FusionTarget;
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// Base class of FusionPredicate, etc. The avaliable variables are:
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// * const TargetInstrInfo &TII
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// * const TargetSubtargetInfo &STI
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// * const MachineRegisterInfo &MRI
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// * const MachineInstr *FirstMI
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// * const MachineInstr &SecondMI
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class FusionPredicate<FusionTarget target> {
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FusionTarget Target = target;
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}
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class FirstFusionPredicate: FusionPredicate<first>;
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class SecondFusionPredicate: FusionPredicate<second>;
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class BothFusionPredicate: FusionPredicate<both>;
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// FusionPredicate with raw code predicate.
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class FusionPredicateWithCode<code pred> : FusionPredicate<both> {
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code Predicate = pred;
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}
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// FusionPredicate with MCInstPredicate.
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class FusionPredicateWithMCInstPredicate<FusionTarget target, MCInstPredicate pred>
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: FusionPredicate<target> {
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MCInstPredicate Predicate = pred;
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}
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class FirstFusionPredicateWithMCInstPredicate<MCInstPredicate pred>
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: FusionPredicateWithMCInstPredicate<first, pred>;
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class SecondFusionPredicateWithMCInstPredicate<MCInstPredicate pred>
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: FusionPredicateWithMCInstPredicate<second, pred>;
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// The pred will be applied on both firstMI and secondMI.
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class BothFusionPredicateWithMCInstPredicate<MCInstPredicate pred>
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: FusionPredicateWithMCInstPredicate<second, pred>;
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// Tie firstOpIdx and secondOpIdx. The operand of `FirstMI` at position
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// `firstOpIdx` should be the same as the operand of `SecondMI` at position
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// `secondOpIdx`.
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class TieReg<int firstOpIdx, int secondOpIdx> : BothFusionPredicate {
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int FirstOpIdx = firstOpIdx;
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int SecondOpIdx = secondOpIdx;
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}
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// A predicate for wildcard. The generated code will be like:
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// ```
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// if (!FirstMI)
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// return ReturnValue;
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// ```
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class WildcardPred<bit ret> : FirstFusionPredicate {
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bit ReturnValue = ret;
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}
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def WildcardFalse : WildcardPred<0>;
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def WildcardTrue : WildcardPred<1>;
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// Indicates that the destination register of `FirstMI` should have one use if
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// it is a virtual register.
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class OneUsePred : FirstFusionPredicate;
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def OneUse : OneUsePred;
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// Handled by MacroFusionPredicatorEmitter backend.
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// The generated predicator will be like:
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// ```
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// bool isNAME(const TargetInstrInfo &TII,
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// const TargetSubtargetInfo &STI,
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// const MachineInstr *FirstMI,
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// const MachineInstr &SecondMI) {
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// auto &MRI = SecondMI.getMF()->getRegInfo();
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// /* Predicates */
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// return true;
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// }
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// ```
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class Fusion<list<FusionPredicate> predicates> {
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list<FusionPredicate> Predicates = predicates;
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}
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// The generated predicator will be like:
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// ```
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// bool isNAME(const TargetInstrInfo &TII,
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// const TargetSubtargetInfo &STI,
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// const MachineInstr *FirstMI,
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// const MachineInstr &SecondMI) {
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// auto &MRI = SecondMI.getMF()->getRegInfo();
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// /* Prolog */
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// /* Predicate for `SecondMI` */
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// /* Wildcard */
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// /* Predicate for `FirstMI` */
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// /* Check One Use */
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// /* Tie registers */
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// /* Epilog */
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// return true;
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// }
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// ```
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class SimpleFusion<MCInstPredicate firstPred, MCInstPredicate secondPred,
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list<FusionPredicate> prolog = [],
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list<FusionPredicate> epilog = []>
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: Fusion<!listconcat(
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prolog,
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[
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SecondFusionPredicateWithMCInstPredicate<secondPred>,
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WildcardTrue,
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FirstFusionPredicateWithMCInstPredicate<firstPred>,
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SecondFusionPredicateWithMCInstPredicate<
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CheckAny<[
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CheckIsVRegOperand<0>,
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CheckSameRegOperand<0, 1>
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]>>,
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OneUse,
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TieReg<0, 1>,
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],
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epilog)>;

‎llvm/utils/TableGen/CMakeLists.txt

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@@ -72,6 +72,7 @@ add_tablegen(llvm-tblgen LLVM
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PredicateExpander.cpp
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PseudoLoweringEmitter.cpp
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CompressInstEmitter.cpp
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MacroFusionPredicatorEmitter.cpp
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RegisterBankEmitter.cpp
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RegisterInfoEmitter.cpp
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SearchableTableEmitter.cpp

‎llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp

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@@ -0,0 +1,204 @@
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//===------ MacroFusionPredicatorEmitter.cpp - Generator for Fusion ------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===---------------------------------------------------------------------===//
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//
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// MacroFusionPredicatorEmitter implements a TableGen-driven predicators
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// generator for macro-op fusions.
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//
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//===---------------------------------------------------------------------===//
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#include "CodeGenTarget.h"
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#include "PredicateExpander.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/TableGenBackend.h"
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#include <set>
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#include <vector>
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using namespace llvm;
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#define DEBUG_TYPE "macro-fusion-predicator"
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namespace {
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class MacroFusionPredicatorEmitter {
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RecordKeeper &Records;
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CodeGenTarget Target;
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void emitMacroFusionDecl(std::vector<Record *> Fusions, PredicateExpander &PE,
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raw_ostream &OS);
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void emitMacroFusionImpl(std::vector<Record *> Fusions, PredicateExpander &PE,
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raw_ostream &OS);
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void emitPredicates(std::vector<Record *> &FirstPredicate,
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PredicateExpander &PE, raw_ostream &OS);
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void emitFirstPredicate(Record *SecondPredicate, PredicateExpander &PE,
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raw_ostream &OS);
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void emitSecondPredicate(Record *SecondPredicate, PredicateExpander &PE,
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raw_ostream &OS);
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void emitBothPredicate(Record *Predicates, PredicateExpander &PE,
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raw_ostream &OS);
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public:
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MacroFusionPredicatorEmitter(RecordKeeper &R) : Records(R), Target(R) {}
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void run(raw_ostream &OS);
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};
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} // End anonymous namespace.
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void MacroFusionPredicatorEmitter::emitMacroFusionDecl(
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std::vector<Record *> Fusions, PredicateExpander &PE, raw_ostream &OS) {
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OS << "#ifdef GET_" << Target.getName() << "_MACRO_FUSION_PRED_DECL\n\n";
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for (Record *Fusion : Fusions) {
58+
OS << "bool is" << Fusion->getName() << "(const TargetInstrInfo &, "
59+
<< "const TargetSubtargetInfo &, "
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<< "const MachineInstr *, "
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<< "const MachineInstr &);\n";
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}
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OS << "\n#endif\n";
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OS << "#undef GET_" << Target.getName() << "_MACRO_FUSION_PRED_DECL\n";
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}
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void MacroFusionPredicatorEmitter::emitMacroFusionImpl(
69+
std::vector<Record *> Fusions, PredicateExpander &PE, raw_ostream &OS) {
70+
OS << "#ifdef GET_" << Target.getName() << "_MACRO_FUSION_PRED_IMPL\n\n";
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for (Record *Fusion : Fusions) {
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std::vector<Record *> Predicates =
74+
Fusion->getValueAsListOfDefs("Predicates");
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OS << "bool is" << Fusion->getName() << "(\n";
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OS.indent(5) << "const TargetInstrInfo &TII,\n";
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OS.indent(5) << "const TargetSubtargetInfo &STI,\n";
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OS.indent(5) << "const MachineInstr *FirstMI,\n";
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OS.indent(5) << "const MachineInstr &SecondMI) {\n";
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OS.indent(2) << "auto &MRI = SecondMI.getMF()->getRegInfo();\n";
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emitPredicates(Predicates, PE, OS);
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OS.indent(2) << "return true;\n";
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OS << "}\n";
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}
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OS << "\n#endif\n";
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OS << "#undef GET_" << Target.getName() << "_MACRO_FUSION_PRED_IMPL\n\n";
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}
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void MacroFusionPredicatorEmitter::emitPredicates(
94+
std::vector<Record *> &Predicates, PredicateExpander &PE, raw_ostream &OS) {
95+
for (Record *Predicate : Predicates) {
96+
Record *Target = Predicate->getValueAsDef("Target");
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if (Target->getName() == "first")
98+
emitFirstPredicate(Predicate, PE, OS);
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else if (Target->getName() == "second")
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emitSecondPredicate(Predicate, PE, OS);
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else if (Target->getName() == "both")
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emitBothPredicate(Predicate, PE, OS);
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else
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PrintFatalError(Target->getLoc(),
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"Unsupported 'FusionTarget': " + Target->getName());
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}
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}
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void MacroFusionPredicatorEmitter::emitFirstPredicate(Record *Predicate,
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PredicateExpander &PE,
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raw_ostream &OS) {
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if (Predicate->isSubClassOf("WildcardPred")) {
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OS.indent(2) << "if (!FirstMI)\n";
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OS.indent(2) << " return "
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<< (Predicate->getValueAsBit("ReturnValue") ? "true" : "false")
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<< ";\n";
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} else if (Predicate->isSubClassOf("OneUsePred")) {
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OS.indent(2) << "{\n";
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OS.indent(4) << "Register FirstDest = FirstMI->getOperand(0).getReg();\n";
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OS.indent(4)
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<< "if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))\n";
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OS.indent(4) << " return false;\n";
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OS.indent(2) << "}\n";
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} else if (Predicate->isSubClassOf(
125+
"FirstFusionPredicateWithMCInstPredicate")) {
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OS.indent(2) << "{\n";
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OS.indent(4) << "const MachineInstr *MI = FirstMI;\n";
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OS.indent(4) << "if (";
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PE.setNegatePredicate(true);
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PE.setIndentLevel(3);
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PE.expandPredicate(OS, Predicate->getValueAsDef("Predicate"));
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OS << ")\n";
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OS.indent(4) << " return false;\n";
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OS.indent(2) << "}\n";
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} else {
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PrintFatalError(Predicate->getLoc(),
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"Unsupported predicate for first instruction: " +
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Predicate->getType()->getAsString());
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}
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}
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void MacroFusionPredicatorEmitter::emitSecondPredicate(Record *Predicate,
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PredicateExpander &PE,
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raw_ostream &OS) {
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if (Predicate->isSubClassOf("SecondFusionPredicateWithMCInstPredicate")) {
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OS.indent(2) << "{\n";
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OS.indent(4) << "const MachineInstr *MI = &SecondMI;\n";
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OS.indent(4) << "if (";
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PE.setNegatePredicate(true);
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PE.setIndentLevel(3);
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PE.expandPredicate(OS, Predicate->getValueAsDef("Predicate"));
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OS << ")\n";
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OS.indent(4) << " return false;\n";
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OS.indent(2) << "}\n";
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} else {
156+
PrintFatalError(Predicate->getLoc(),
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"Unsupported predicate for first instruction: " +
158+
Predicate->getType()->getAsString());
159+
}
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}
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void MacroFusionPredicatorEmitter::emitBothPredicate(Record *Predicate,
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PredicateExpander &PE,
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raw_ostream &OS) {
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if (Predicate->isSubClassOf("FusionPredicateWithCode"))
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OS << Predicate->getValueAsString("Predicate");
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else if (Predicate->isSubClassOf("BothFusionPredicateWithMCInstPredicate")) {
168+
Record *MCPred = Predicate->getValueAsDef("Predicate");
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emitFirstPredicate(MCPred, PE, OS);
170+
emitSecondPredicate(MCPred, PE, OS);
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} else if (Predicate->isSubClassOf("TieReg")) {
172+
int FirstOpIdx = Predicate->getValueAsInt("FirstOpIdx");
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int SecondOpIdx = Predicate->getValueAsInt("SecondOpIdx");
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OS.indent(2) << "if (!(FirstMI->getOperand(" << FirstOpIdx
175+
<< ").isReg() &&\n";
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OS.indent(2) << " SecondMI.getOperand(" << SecondOpIdx
177+
<< ").isReg() &&\n";
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OS.indent(2) << " FirstMI->getOperand(" << FirstOpIdx
179+
<< ").getReg() == SecondMI.getOperand(" << SecondOpIdx
180+
<< ").getReg()))\n";
181+
OS.indent(2) << " return false;\n";
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} else
183+
PrintFatalError(Predicate->getLoc(),
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"Unsupported predicate for both instruction: " +
185+
Predicate->getType()->getAsString());
186+
}
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void MacroFusionPredicatorEmitter::run(raw_ostream &OS) {
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// Emit file header.
190+
emitSourceFileHeader("Macro Fusion Predicators", OS);
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PredicateExpander PE(Target.getName());
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PE.setByRef(false);
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PE.setExpandForMC(false);
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196+
std::vector<Record *> Fusions = Records.getAllDerivedDefinitions("Fusion");
197+
// Sort macro fusions by name.
198+
sort(Fusions, LessRecord());
199+
emitMacroFusionDecl(Fusions, PE, OS);
200+
emitMacroFusionImpl(Fusions, PE, OS);
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}
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203+
static TableGen::Emitter::OptClass<MacroFusionPredicatorEmitter>
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X("gen-macro-fusion-pred", "Generate macro fusion predicators.");

‎llvm/utils/TableGen/PredicateExpander.cpp

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@@ -194,6 +194,11 @@ void PredicateExpander::expandCheckIsRegOperand(raw_ostream &OS, int OpIndex) {
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<< "getOperand(" << OpIndex << ").isReg() ";
195195
}
196196

197+
void PredicateExpander::expandCheckIsVRegOperand(raw_ostream &OS, int OpIndex) {
198+
OS << (shouldNegate() ? "!" : "") << "MI" << (isByRef() ? "." : "->")
199+
<< "getOperand(" << OpIndex << ").getReg().isVirtual()";
200+
}
201+
197202
void PredicateExpander::expandCheckIsImmOperand(raw_ostream &OS, int OpIndex) {
198203
OS << (shouldNegate() ? "!" : "") << "MI" << (isByRef() ? "." : "->")
199204
<< "getOperand(" << OpIndex << ").isImm() ";
@@ -319,6 +324,9 @@ void PredicateExpander::expandPredicate(raw_ostream &OS, const Record *Rec) {
319324
if (Rec->isSubClassOf("CheckIsRegOperand"))
320325
return expandCheckIsRegOperand(OS, Rec->getValueAsInt("OpIndex"));
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327+
if (Rec->isSubClassOf("CheckIsVRegOperand"))
328+
return expandCheckIsVRegOperand(OS, Rec->getValueAsInt("OpIndex"));
329+
322330
if (Rec->isSubClassOf("CheckIsImmOperand"))
323331
return expandCheckIsImmOperand(OS, Rec->getValueAsInt("OpIndex"));
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‎llvm/utils/TableGen/PredicateExpander.h

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@@ -75,6 +75,7 @@ class PredicateExpander {
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bool IsCheckAll);
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void expandTIIFunctionCall(raw_ostream &OS, StringRef MethodName);
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void expandCheckIsRegOperand(raw_ostream &OS, int OpIndex);
78+
void expandCheckIsVRegOperand(raw_ostream &OS, int OpIndex);
7879
void expandCheckIsImmOperand(raw_ostream &OS, int OpIndex);
7980
void expandCheckInvalidRegOperand(raw_ostream &OS, int OpIndex);
8081
void expandCheckFunctionPredicate(raw_ostream &OS, StringRef MCInstFn,

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