llvm can't correctly support 'H', 'Q' and 'R' modifiers. Just mark it an error.

llvm-svn: 104891

Author: Evan Cheng

llvm/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp

@@ -1064,27 +1064,11 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
       printOperand(MI, OpNum, O);
       return false;
     case 'Q':
-      // Print the least significant half of a register pair.
-      if (TM.getTargetData()->isBigEndian())
-        break;
-      printOperand(MI, OpNum, O);
-      return false;
     case 'R':
-      // Print the most significant half of a register pair.
-      if (TM.getTargetData()->isLittleEndian())
-        break;
-      printOperand(MI, OpNum, O);
-      return false;
     case 'H':
-      break;
-    }
-    // Print the second half of a register pair (for 'Q', 'R' or 'H').
-    // Verify that this operand has two consecutive registers.
-    if (!MI->getOperand(OpNum).isReg() ||
-        OpNum+1 == MI->getNumOperands() ||
-        !MI->getOperand(OpNum+1).isReg())
+      llvm_unreachable("llvm does not support 'Q', 'R', and 'H' modifiers!");
       return true;
-    ++OpNum;
+    }
   }
 
   printOperand(MI, OpNum, O);

llvm/test/CodeGen/ARM/inlineasm.ll

@@ -6,14 +6,6 @@ define i32 @test1(i32 %tmp54) {
 }
 
 define void @test2() {
-	%tmp1 = call i64 asm "ldmia $1!, {$0, ${0:H}}", "=r,=*r,1"( i32** null, i32* null )		; <i64> [#uses=2]
-	%tmp2 = lshr i64 %tmp1, 32		; <i64> [#uses=1]
-	%tmp3 = trunc i64 %tmp2 to i32		; <i32> [#uses=1]
-	%tmp4 = call i32 asm "pkhbt $0, $1, $2, lsl #16", "=r,r,r"( i32 0, i32 %tmp3 )		; <i32> [#uses=0]
-	ret void
-}
-
-define void @test3() {
 	tail call void asm sideeffect "/* number: ${0:c} */", "i"( i32 1 )
 	ret void
 }