@@ -2949,3 +2949,48 @@ entry:
2949
2949
%4 = shl i64 %3 , 4
2950
2950
ret i64 %4
2951
2951
}
2952
+
2953
+ define i64 @srli_slliuw_2 (i64 %1 ) {
2954
+ ; RV64I-LABEL: srli_slliuw_2:
2955
+ ; RV64I: # %bb.0: # %entry
2956
+ ; RV64I-NEXT: srli a0, a0, 15
2957
+ ; RV64I-NEXT: li a1, 1
2958
+ ; RV64I-NEXT: slli a1, a1, 35
2959
+ ; RV64I-NEXT: addi a1, a1, -8
2960
+ ; RV64I-NEXT: and a0, a0, a1
2961
+ ; RV64I-NEXT: ret
2962
+ ;
2963
+ ; RV64ZBA-LABEL: srli_slliuw_2:
2964
+ ; RV64ZBA: # %bb.0: # %entry
2965
+ ; RV64ZBA-NEXT: srli a0, a0, 15
2966
+ ; RV64ZBA-NEXT: srli a0, a0, 3
2967
+ ; RV64ZBA-NEXT: slli.uw a0, a0, 3
2968
+ ; RV64ZBA-NEXT: ret
2969
+ entry:
2970
+ %2 = lshr i64 %1 , 18
2971
+ %3 = and i64 %2 , 4294967295
2972
+ %4 = shl i64 %3 , 3
2973
+ ret i64 %4
2974
+ }
2975
+
2976
+ define i64 @srli_slliuw_canonical_2 (i64 %0 ) {
2977
+ ; RV64I-LABEL: srli_slliuw_canonical_2:
2978
+ ; RV64I: # %bb.0: # %entry
2979
+ ; RV64I-NEXT: srli a0, a0, 15
2980
+ ; RV64I-NEXT: li a1, 1
2981
+ ; RV64I-NEXT: slli a1, a1, 35
2982
+ ; RV64I-NEXT: addi a1, a1, -8
2983
+ ; RV64I-NEXT: and a0, a0, a1
2984
+ ; RV64I-NEXT: ret
2985
+ ;
2986
+ ; RV64ZBA-LABEL: srli_slliuw_canonical_2:
2987
+ ; RV64ZBA: # %bb.0: # %entry
2988
+ ; RV64ZBA-NEXT: srli a0, a0, 15
2989
+ ; RV64ZBA-NEXT: srli a0, a0, 3
2990
+ ; RV64ZBA-NEXT: slli.uw a0, a0, 3
2991
+ ; RV64ZBA-NEXT: ret
2992
+ entry:
2993
+ %1 = lshr i64 %0 , 15
2994
+ %2 = and i64 %1 , 34359738360
2995
+ ret i64 %2
2996
+ }
0 commit comments