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[NFC][AMDGPU] Pre-commit a test case for v_pk_mov_b32 in vgpr-remat.mir
This PR serves as a preliminary step, adding a test case for `v_pk_mov_b32` in `vgpr-remat.mir`. It is intended to demonstrate the code changes introduced in an upcoming PR.
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llvm/test/CodeGen/AMDGPU/vgpr-remat.mir

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@@ -46,3 +46,50 @@ body: |
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%4.sub1:vreg_96 = COPY %2:vgpr_32
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S_ENDPGM 0, implicit %4
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...
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---
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name: test_remat_v_pk_mov_b32
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: test_remat_v_pk_mov_b32
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $sgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[V_PK_MOV_B32_:%[0-9]+]]:vreg_64_align2 = V_PK_MOV_B32 8, 0, 8, 0, 0, 0, 0, 0, 0, implicit $exec
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY [[V_PK_MOV_B32_]]
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY [[V_PK_MOV_B32_]]
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr0
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; CHECK-NEXT: $exec = S_MOV_B64_term [[COPY2]]
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; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
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; CHECK-NEXT: S_BRANCH %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = V_PK_ADD_F32 8, [[COPY]], 8, [[COPY]], 11, 0, 0, 0, 0, implicit $mode, implicit $exec
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = V_PK_ADD_F32 8, [[COPY1]], 8, [[COPY1]], 11, 0, 0, 0, 0, implicit $mode, implicit $exec
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: S_NOP 0, implicit [[COPY]]
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; CHECK-NEXT: S_NOP 0, implicit [[COPY1]]
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; CHECK-NEXT: S_ENDPGM 0, implicit [[V_PK_MOV_B32_]]
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bb.0:
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liveins: $sgpr0
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%0:vreg_64_align2 = V_PK_MOV_B32 8, 0, 8, 0, 0, 0, 0, 0, 0, implicit $exec
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%1:vreg_64_align2 = COPY %0:vreg_64_align2
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%2:vreg_64_align2 = COPY %0:vreg_64_align2
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%3:sreg_64 = COPY $sgpr0
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$exec = S_MOV_B64_term %3:sreg_64
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S_CBRANCH_EXECZ %bb.2, implicit $exec
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S_BRANCH %bb.1
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bb.1:
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%1:vreg_64_align2 = V_PK_ADD_F32 8, %1, 8, %1, 11, 0, 0, 0, 0, implicit $mode, implicit $exec
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%2:vreg_64_align2 = V_PK_ADD_F32 8, %2, 8, %2, 11, 0, 0, 0, 0, implicit $mode, implicit $exec
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bb.2:
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S_NOP 0, implicit %1
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S_NOP 0, implicit %2
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S_ENDPGM 0, implicit %0
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...

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