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[AMDGPU] Support arbitrary types in amdgcn.dead (#134841)
Legalize the amdgcn.dead intrinsic to work with types other than i32. It still generates IMPLICIT_DEFs. Remove some of the previous code for selecting/reg bank mapping it for 32-bit types, since everything is done in the legalizer now.
1 parent 07bc54b commit 45d96df

7 files changed

+1045
-17
lines changed

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1191,12 +1191,6 @@ bool AMDGPUInstructionSelector::selectG_INTRINSIC(MachineInstr &I) const {
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case Intrinsic::amdgcn_permlane16_swap:
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case Intrinsic::amdgcn_permlane32_swap:
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return selectPermlaneSwapIntrin(I, IntrinsicID);
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case Intrinsic::amdgcn_dead: {
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I.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF));
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I.removeOperand(1); // drop intrinsic ID
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return RBI.constrainGenericRegister(I.getOperand(0).getReg(),
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AMDGPU::VGPR_32RegClass, *MRI);
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}
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default:
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return selectImpl(I, *CoverageInfo);
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}

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

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Original file line numberDiff line numberDiff line change
@@ -7658,6 +7658,13 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
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return legalizeLaneOp(Helper, MI, IntrID);
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case Intrinsic::amdgcn_s_buffer_prefetch_data:
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return legalizeSBufferPrefetch(Helper, MI);
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case Intrinsic::amdgcn_dead: {
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// TODO: Use poison instead of undef
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for (const MachineOperand &Def : MI.defs())
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B.buildUndef(Def);
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MI.eraseFromParent();
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return true;
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}
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default: {
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if (const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr =
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AMDGPU::getImageDimIntrinsicInfo(IntrID))

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4698,7 +4698,6 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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case Intrinsic::amdgcn_set_inactive_chain_arg:
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case Intrinsic::amdgcn_permlane64:
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case Intrinsic::amdgcn_ds_bpermute_fi_b32:
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case Intrinsic::amdgcn_dead:
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return getDefaultMappingAllVGPR(MI);
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case Intrinsic::amdgcn_cvt_pkrtz:
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if (Subtarget.hasSALUFloatInsts() && isSALUMapping(MI))

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6628,6 +6628,11 @@ void SITargetLowering::ReplaceNodeResults(SDNode *N,
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Results.push_back(LoadVal);
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return;
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}
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case Intrinsic::amdgcn_dead: {
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for (unsigned I = 0, E = N->getNumValues(); I < E; ++I)
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Results.push_back(DAG.getPOISON(N->getValueType(I)));
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return;
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}
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}
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break;
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}
@@ -9113,6 +9118,12 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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case Intrinsic::amdgcn_mov_dpp8:
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case Intrinsic::amdgcn_update_dpp:
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return lowerLaneOp(*this, Op.getNode(), DAG);
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case Intrinsic::amdgcn_dead: {
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SmallVector<SDValue, 8> Poisons;
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for (const EVT ValTy : Op.getNode()->values())
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Poisons.push_back(DAG.getPOISON(ValTy));
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return DAG.getMergeValues(Poisons, SDLoc(Op));
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}
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default:
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if (const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr =
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AMDGPU::getImageDimIntrinsicInfo(IntrinsicID))

llvm/lib/Target/AMDGPU/SIInstructions.td

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4510,9 +4510,3 @@ def V_ILLEGAL : Enc32, InstSI<(outs), (ins), "v_illegal"> {
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let hasSideEffects = 1;
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let SubtargetPredicate = isGFX10Plus;
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}
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// FIXME: Would be nice if we could set the register class for the destination
4515-
// register too.
4516-
def IMP_DEF_FROM_INTRINSIC: Pat<
4517-
(i32 (int_amdgcn_dead)), (IMPLICIT_DEF)>;
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Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,32 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=amdgcn-amdpal -mcpu=gfx1200 -run-pass=legalizer %s -o - | FileCheck %s
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---
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name: test_struct
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body: |
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bb.1.entry:
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; CHECK-LABEL: name: test_struct
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; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
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; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
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; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
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; CHECK-NEXT: [[DEF3:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
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; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](<3 x s32>)
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; CHECK-NEXT: $vgpr0 = COPY [[DEF]](s32)
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; CHECK-NEXT: $vgpr1 = COPY [[UV]](s32)
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; CHECK-NEXT: $vgpr2 = COPY [[UV1]](s32)
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; CHECK-NEXT: $vgpr3 = COPY [[UV2]](s32)
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; CHECK-NEXT: $vgpr4_vgpr5 = COPY [[DEF2]](s64)
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; CHECK-NEXT: $vgpr6 = COPY [[DEF3]](<2 x s16>)
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; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
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%0:_(s32), %1:_(<3 x s32>), %2:_(s64), %3:_(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.dead)
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%4:_(s32), %5:_(s32), %6:_(s32) = G_UNMERGE_VALUES %1(<3 x s32>)
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$vgpr0 = COPY %0(s32)
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$vgpr1 = COPY %4(s32)
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$vgpr2 = COPY %5(s32)
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$vgpr3 = COPY %6(s32)
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$vgpr4_vgpr5 = COPY %2(s64)
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$vgpr6 = COPY %3(<2 x s16>)
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SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
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...

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