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RegisterCoalescer: Set undef on full register uses when coalescing implicit_def (#118321)
Previously this would delete the IMPLICIT_DEF and not introduce the undef flag on the use operand. Fixes sub-issue found while reducing #109294
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2 files changed

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llvm/lib/CodeGen/RegisterCoalescer.cpp

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1842,9 +1842,12 @@ void RegisterCoalescer::updateRegDefsUses(Register SrcReg, Register DstReg,
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if (DstInt && DstInt->hasSubRanges() && DstReg != SrcReg) {
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for (MachineOperand &MO : MRI->reg_operands(DstReg)) {
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if (MO.isUndef())
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continue;
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unsigned SubReg = MO.getSubReg();
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if (SubReg == 0 || MO.isUndef())
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if (SubReg == 0 && MO.isDef())
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continue;
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MachineInstr &MI = *MO.getParent();
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if (MI.isDebugInstr())
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continue;
Lines changed: 43 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,43 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=register-coalescer -verify-coalescing -o - %s | FileCheck %s
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# Make sure that the undef flag is set on %0 after the IMPLICIT_DEF is
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# deleted when coalescing %0 with %1
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---
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name: test
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tracksRegLiveness: true
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machineFunctionInfo:
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stackPtrOffsetReg: '$sgpr32'
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body: |
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bb.0:
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; CHECK-LABEL: name: test
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; CHECK: [[S_BUFFER_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_IMM undef %0, 36, 0 :: (dereferenceable invariant load (s64))
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; CHECK-NEXT: undef [[S_ADD_U32_:%[0-9]+]].sub1:sgpr_128 = S_ADD_U32 [[S_BUFFER_LOAD_DWORDX2_IMM]].sub0, 32, implicit-def dead $scc
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; CHECK-NEXT: SI_RETURN implicit [[S_ADD_U32_]].sub1
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%0:sgpr_128 = IMPLICIT_DEF
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%1:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_IMM %0, 36, 0 :: (dereferenceable invariant load (s64))
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%2:sreg_32 = S_ADD_U32 %1.sub0, 32, implicit-def dead $scc
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%0.sub1:sgpr_128 = COPY killed %2
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SI_RETURN implicit %0.sub1
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...
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---
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name: test_w_undef_dead
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tracksRegLiveness: true
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machineFunctionInfo:
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stackPtrOffsetReg: '$sgpr32'
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body: |
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bb.0:
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; CHECK-LABEL: name: test_w_undef_dead
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; CHECK: dead [[S_BUFFER_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_IMM undef %0, 36, 0 :: (dereferenceable invariant load (s64))
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; CHECK-NEXT: undef [[S_ADD_U32_:%[0-9]+]].sub1:sgpr_128 = S_ADD_U32 undef [[S_BUFFER_LOAD_DWORDX2_IMM]].sub0, 32, implicit-def dead $scc
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; CHECK-NEXT: SI_RETURN implicit [[S_ADD_U32_]].sub1
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%0:sgpr_128 = IMPLICIT_DEF
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dead %1:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_IMM %0, 36, 0 :: (dereferenceable invariant load (s64))
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%2:sreg_32 = S_ADD_U32 undef %1.sub0, 32, implicit-def dead $scc
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%0.sub1:sgpr_128 = COPY killed %2
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SI_RETURN implicit %0.sub1
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...

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