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[X86] checkBitcastSrcVectorSize - early return when reach to MaxRecursionDepth. (#130226)
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+18
-10
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+18
-10
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llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 18 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -44735,7 +44735,10 @@ bool X86TargetLowering::isSplatValueForTargetNode(SDValue Op,
4473544735
// Helper to peek through bitops/trunc/setcc to determine size of source vector.
4473644736
// Allows combineBitcastvxi1 to determine what size vector generated a <X x i1>.
4473744737
static bool checkBitcastSrcVectorSize(SDValue Src, unsigned Size,
44738-
bool AllowTruncate) {
44738+
bool AllowTruncate, unsigned Depth) {
44739+
// Limit recursion.
44740+
if (Depth >= SelectionDAG::MaxRecursionDepth)
44741+
return false;
4473944742
switch (Src.getOpcode()) {
4474044743
case ISD::TRUNCATE:
4474144744
if (!AllowTruncate)
@@ -44744,17 +44747,22 @@ static bool checkBitcastSrcVectorSize(SDValue Src, unsigned Size,
4474444747
case ISD::SETCC:
4474544748
return Src.getOperand(0).getValueSizeInBits() == Size;
4474644749
case ISD::FREEZE:
44747-
return checkBitcastSrcVectorSize(Src.getOperand(0), Size, AllowTruncate);
44750+
return checkBitcastSrcVectorSize(Src.getOperand(0), Size, AllowTruncate,
44751+
Depth + 1);
4474844752
case ISD::AND:
4474944753
case ISD::XOR:
4475044754
case ISD::OR:
44751-
return checkBitcastSrcVectorSize(Src.getOperand(0), Size, AllowTruncate) &&
44752-
checkBitcastSrcVectorSize(Src.getOperand(1), Size, AllowTruncate);
44755+
return checkBitcastSrcVectorSize(Src.getOperand(0), Size, AllowTruncate,
44756+
Depth + 1) &&
44757+
checkBitcastSrcVectorSize(Src.getOperand(1), Size, AllowTruncate,
44758+
Depth + 1);
4475344759
case ISD::SELECT:
4475444760
case ISD::VSELECT:
4475544761
return Src.getOperand(0).getScalarValueSizeInBits() == 1 &&
44756-
checkBitcastSrcVectorSize(Src.getOperand(1), Size, AllowTruncate) &&
44757-
checkBitcastSrcVectorSize(Src.getOperand(2), Size, AllowTruncate);
44762+
checkBitcastSrcVectorSize(Src.getOperand(1), Size, AllowTruncate,
44763+
Depth + 1) &&
44764+
checkBitcastSrcVectorSize(Src.getOperand(2), Size, AllowTruncate,
44765+
Depth + 1);
4475844766
case ISD::BUILD_VECTOR:
4475944767
return ISD::isBuildVectorAllZeros(Src.getNode()) ||
4476044768
ISD::isBuildVectorAllOnes(Src.getNode());
@@ -44925,7 +44933,7 @@ static SDValue combineBitcastvxi1(SelectionDAG &DAG, EVT VT, SDValue Src,
4492544933
// For cases such as (i4 bitcast (v4i1 setcc v4i64 v1, v2))
4492644934
// sign-extend to a 256-bit operation to avoid truncation.
4492744935
if (Subtarget.hasAVX() &&
44928-
checkBitcastSrcVectorSize(Src, 256, Subtarget.hasAVX2())) {
44936+
checkBitcastSrcVectorSize(Src, 256, Subtarget.hasAVX2(), 0)) {
4492944937
SExtVT = MVT::v4i64;
4493044938
PropagateSExt = true;
4493144939
}
@@ -44937,8 +44945,8 @@ static SDValue combineBitcastvxi1(SelectionDAG &DAG, EVT VT, SDValue Src,
4493744945
// If the setcc operand is 128-bit, prefer sign-extending to 128-bit over
4493844946
// 256-bit because the shuffle is cheaper than sign extending the result of
4493944947
// the compare.
44940-
if (Subtarget.hasAVX() && (checkBitcastSrcVectorSize(Src, 256, true) ||
44941-
checkBitcastSrcVectorSize(Src, 512, true))) {
44948+
if (Subtarget.hasAVX() && (checkBitcastSrcVectorSize(Src, 256, true, 0) ||
44949+
checkBitcastSrcVectorSize(Src, 512, true, 0))) {
4494244950
SExtVT = MVT::v8i32;
4494344951
PropagateSExt = true;
4494444952
}
@@ -44963,7 +44971,7 @@ static SDValue combineBitcastvxi1(SelectionDAG &DAG, EVT VT, SDValue Src,
4496344971
break;
4496444972
}
4496544973
// Split if this is a <64 x i8> comparison result.
44966-
if (checkBitcastSrcVectorSize(Src, 512, false)) {
44974+
if (checkBitcastSrcVectorSize(Src, 512, false, 0)) {
4496744975
SExtVT = MVT::v64i8;
4496844976
break;
4496944977
}

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