Allow th=3 for SCOPE_SYS

Author: mbrkusanin

llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp

@@ -602,10 +602,6 @@ class SIGfx12CacheControl : public SIGfx11CacheControl {
   // MI. \returns Returns true if \p MI is modified, false otherwise.
   bool setScope(const MachineBasicBlock::iterator MI,
                 AMDGPU::CPol::CPol Value) const;
-  // Checks if CPol operand is present in instruction \p MI and if current Scope
-  // policy is same as \p Value.
-  bool isScope(const MachineBasicBlock::iterator MI,
-               AMDGPU::CPol::CPol Value) const;
 
   // Stores with system scope (SCOPE_SYS) need to wait for:
   // - loads or atomics(returning) - wait for {LOAD|SAMPLE|BVH|KM}CNT==0
@@ -2227,15 +2223,6 @@ bool SIGfx12CacheControl::setScope(const MachineBasicBlock::iterator MI,
   return false;
 }
 
-bool SIGfx12CacheControl::isScope(const MachineBasicBlock::iterator MI,
-                                  AMDGPU::CPol::CPol Value) const {
-  MachineOperand *CPol = TII->getNamedOperand(*MI, OpName::cpol);
-  if (!CPol)
-    return false;
-
-  return (CPol->getImm() & AMDGPU::CPol::SCOPE) == Value;
-}
-
 bool SIGfx12CacheControl::insertWaitsBeforeSystemScopeStore(
     const MachineBasicBlock::iterator MI) const {
   // TODO: implement flag for frontend to give us a hint not to insert waits.
@@ -2445,11 +2432,7 @@ bool SIGfx12CacheControl::enableVolatileAndOrNonTemporal(
 bool SIGfx12CacheControl::enableLastUse(MachineInstr &MI,
                                         bool IsLastUse) const {
   assert(MI.mayLoad() && !MI.mayStore());
-
-  if (IsLastUse && !isScope(MI, AMDGPU::CPol::SCOPE_SYS))
-    return setTH(MI, AMDGPU::CPol::TH_LU);
-
-  return false;
+  return IsLastUse ? setTH(MI, AMDGPU::CPol::TH_LU) : false;
 }
 
 bool SIGfx12CacheControl::expandSystemScopeStore(

llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll

@@ -47,7 +47,7 @@ define amdgpu_kernel void @flat_last_use_volatile_load(ptr %in, ptr %out) {
 ; GFX12-NEXT:    s_load_b128 s[0:3], s[0:1], 0x0
 ; GFX12-NEXT:    s_wait_kmcnt 0x0
 ; GFX12-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX12-NEXT:    flat_load_b32 v2, v[0:1] scope:SCOPE_SYS
+; GFX12-NEXT:    flat_load_b32 v2, v[0:1] th:TH_LOAD_BYPASS scope:SCOPE_SYS
 ; GFX12-NEXT:    s_wait_loadcnt 0x0
 ; GFX12-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
 ; GFX12-NEXT:    s_wait_dscnt 0x0

llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll

@@ -46,7 +46,7 @@ define amdgpu_kernel void @global_last_use_volatile_load(ptr addrspace(1) %in, p
 ; GFX12-NEXT:    s_load_b128 s[0:3], s[0:1], 0x0
 ; GFX12-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_b32 v1, v0, s[0:1] scope:SCOPE_SYS
+; GFX12-NEXT:    global_load_b32 v1, v0, s[0:1] th:TH_LOAD_BYPASS scope:SCOPE_SYS
 ; GFX12-NEXT:    s_wait_loadcnt 0x0
 ; GFX12-NEXT:    global_store_b32 v0, v1, s[2:3]
 ; GFX12-NEXT:    s_nop 0

llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll

@@ -51,7 +51,7 @@ define amdgpu_kernel void @private_nontemporal_volatile_load(ptr addrspace(5) %i
 ; GFX12-NEXT:    s_load_b64 s[0:1], s[0:1], 0x8
 ; GFX12-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    scratch_load_b32 v0, off, s2 scope:SCOPE_SYS
+; GFX12-NEXT:    scratch_load_b32 v0, off, s2 th:TH_LOAD_BYPASS scope:SCOPE_SYS
 ; GFX12-NEXT:    s_wait_loadcnt 0x0
 ; GFX12-NEXT:    global_store_b32 v1, v0, s[0:1]
 ; GFX12-NEXT:    s_nop 0