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[TableGen][GISel] Remove check for LLT when emitting renderers (#121144)
Types used in the destination DAG of a pattern should not matter for GlobalISel. All necessary checks are emitted in the form of matchers when traversing the source DAG. In particular, the check prevented importing patterns containing iPTR in the middle of the destination DAG. This reduces the number of skipped patterns on Mips and RISCV: ``` Mips 1270 -> 1212 (-58) RISCV 42165 -> 42088 (-77) ``` Most of these patterns are for atomic operations.
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-13
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llvm/test/TableGen/GlobalISelEmitter/OverloadedPtr.td

Lines changed: 22 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4,10 +4,32 @@
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include "llvm/Target/Target.td"
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include "GlobalISelEmitterCommon.td"
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7+
def GPR : RegisterClass<"MyTarget", [i32, i64], 32, (add R0)>;
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let TargetPrefix = "mytarget" in {
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def int_mytarget_anyptr : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
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}
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// Check that iPTR in the destination DAG doesn't prevent the pattern from being imported.
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// CHECK: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
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// CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
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// CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
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// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
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// CHECK-NEXT: // MIs[0] src1
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// CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
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// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID),
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// CHECK-NEXT: // (ld:{ *:[i32] } GPR:{ *:[iPTR] }:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (ANYLOAD:{ *:[i32] } GPR:{ *:[iPTR] }:$src1)
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// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::ANYLOAD),
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// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
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// CHECK-NEXT: // GIR_Coverage, 0,
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// CHECK-NEXT: GIR_Done,
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let hasSideEffects = 1 in {
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def ANYLOAD : I<(outs GPR32:$dst), (ins GPR:$src1),
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[(set GPR32:$dst, (load GPR:$src1))]>;
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}
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// Ensure that llvm_anyptr_ty on an intrinsic results in a
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// GIM_CheckPointerToAny rather than a GIM_CheckType.
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//
@@ -20,10 +42,6 @@ let TargetPrefix = "mytarget" in {
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// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_frag_anyptr),
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// CHECK-NEXT: // (intrinsic_w_chain:{ *:[i32] } {{[0-9]+}}:{ *:[iPTR] }, GPR32:{ *:[i32] }:$src)<<P:Predicate_frag_anyptr>> => (ANYLOAD:{ *:[i32] } GPR32:{ *:[i32] }:$src)
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// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::ANYLOAD),
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let hasSideEffects = 1 in {
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def ANYLOAD : I<(outs GPR32:$dst), (ins GPR32:$src1),
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[(set GPR32:$dst, (load GPR32:$src1))]>;
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}
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def frag_anyptr : PatFrag<(ops node:$src),
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(int_mytarget_anyptr node:$src),

llvm/utils/TableGen/GlobalISelEmitter.cpp

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1246,15 +1246,6 @@ Error GlobalISelEmitter::importNamedNodeRenderer(
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if (N.getNumResults() != 1)
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return failedImport("node does not have one result " + to_string(N));
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1249-
std::optional<LLTCodeGen> OpTyOrNone;
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ArrayRef<TypeSetByHwMode> ChildTypes = N.getExtTypes();
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if (ChildTypes.front().isMachineValueType())
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OpTyOrNone = MVTToLLT(ChildTypes.front().getMachineValueType().SimpleTy);
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// TODO: Remove this check. Types in the destination DAG should not matter.
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if (!OpTyOrNone)
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return failedImport("node has unsupported type " + to_string(N));
1257-
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if (R->isSubClassOf("ComplexPattern")) {
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auto I = ComplexPatternEquivs.find(R);
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if (I == ComplexPatternEquivs.end())

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