Updated the MBB-liveins to track liveRegUnits's Root registers and their

respective use-sites

Author: vg0204

llvm/include/llvm/CodeGen/LivePhysRegs.h

@@ -202,14 +202,12 @@ bool isPhysRegUsedAfter(Register Reg, MachineBasicBlock::iterator MBI);
 /// any changes were made.
 static inline bool recomputeLiveIns(MachineBasicBlock &MBB) {
   LivePhysRegs LPR;
-  std::vector<MachineBasicBlock::RegisterMaskPair> OldLiveIns;
+  DenseSet<MCRegister> OldLiveIns;
 
   MBB.clearLiveIns(OldLiveIns);
   computeAndAddLiveIns(LPR, MBB);
-  MBB.sortUniqueLiveIns();
 
-  const std::vector<MachineBasicBlock::RegisterMaskPair> &NewLiveIns =
-      MBB.getLiveIns();
+  const DenseSet<MCRegister> &NewLiveIns = MBB.getLiveIns();
   return OldLiveIns != NewLiveIns;
 }
 

llvm/include/llvm/CodeGen/MachineBasicBlock.h

@@ -15,6 +15,7 @@
 
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/DenseMapInfo.h"
+#include "llvm/ADT/DenseSet.h"
 #include "llvm/ADT/GraphTraits.h"
 #include "llvm/ADT/SparseBitVector.h"
 #include "llvm/ADT/ilist.h"
@@ -175,12 +176,7 @@ class MachineBasicBlock
   std::optional<uint64_t> IrrLoopHeaderWeight;
 
   /// Keep track of the physical registers that are livein of the basicblock.
-  using LiveInVector = std::vector<RegisterMaskPair>;
-  LiveInVector LiveIns;
-
-  /// Keeps track of live register units for those physical registers which
-  /// are livein of the basicblock.
-  BitVector LiveInRegUnits;
+  DenseSet<MCRegister> LiveIns;
 
   /// Alignment of the basic block. One if the basic block does not need to be
   /// aligned.
@@ -466,34 +462,17 @@ class MachineBasicBlock
 
   // LiveIn management methods.
 
-  /// Adds the specified register as a live in. Note that it is an error to add
-  /// the same register to the same set more than once unless the intention is
-  /// to call sortUniqueLiveIns after all registers are added.
+  /// Adds the live regUnits(both of its roots registers) as the live in, based
+  /// on the LaneMask.
   void addLiveIn(MCRegister PhysReg,
-                 LaneBitmask LaneMask = LaneBitmask::getAll()) {
-    LiveIns.push_back(RegisterMaskPair(PhysReg, LaneMask));
-    addLiveInRegUnit(PhysReg, LaneMask);
-  }
-  void addLiveIn(const RegisterMaskPair &RegMaskPair) {
-    LiveIns.push_back(RegMaskPair);
-    addLiveInRegUnit(RegMaskPair.PhysReg, RegMaskPair.LaneMask);
-  }
-
-  // Sets the register units for Reg based on the LaneMask in the
-  // LiveInRegUnits.
-  void addLiveInRegUnit(MCRegister Reg, LaneBitmask LaneMask);
-
-  /// Sorts and uniques the LiveIns vector. It can be significantly faster to do
-  /// this than repeatedly calling isLiveIn before calling addLiveIn for every
-  /// LiveIn insertion.
-  void sortUniqueLiveIns();
+                 LaneBitmask LaneMask = LaneBitmask::getAll());
 
   /// Clear live in list.
   void clearLiveIns();
 
   /// Clear the live in list, and return the removed live in's in \p OldLiveIns.
   /// Requires that the vector \p OldLiveIns is empty.
-  void clearLiveIns(std::vector<RegisterMaskPair> &OldLiveIns);
+  void clearLiveIns(DenseSet<MCRegister> &OldLiveIns);
 
   /// Add PhysReg as live in to this block, and ensure that there is a copy of
   /// PhysReg to a virtual register of class RC. Return the virtual register
@@ -504,16 +483,13 @@ class MachineBasicBlock
   void removeLiveIn(MCRegister Reg,
                     LaneBitmask LaneMask = LaneBitmask::getAll());
 
-  /// Resets the register units from LiveInRegUnits for the specified regsiters.
-  void removeLiveInRegUnit(MCRegister Reg);
-
   /// Return true if the specified register is in the live in set.
   bool isLiveIn(MCRegister Reg,
                 LaneBitmask LaneMask = LaneBitmask::getAll()) const;
 
   // Iteration support for live in sets.  These sets are kept in sorted
   // order by their register number.
-  using livein_iterator = LiveInVector::const_iterator;
+  using livein_iterator = DenseSet<MCRegister>::const_iterator;
 
   /// Unlike livein_begin, this method does not check that the liveness
   /// information is accurate. Still for debug purposes it may be useful
@@ -534,15 +510,15 @@ class MachineBasicBlock
   /// Remove entry from the livein set and return iterator to the next.
   livein_iterator removeLiveIn(livein_iterator I);
 
-  const std::vector<RegisterMaskPair> &getLiveIns() const { return LiveIns; }
+  const DenseSet<MCRegister> &getLiveIns() const { return LiveIns; }
 
   class liveout_iterator {
   public:
     using iterator_category = std::input_iterator_tag;
     using difference_type = std::ptrdiff_t;
-    using value_type = RegisterMaskPair;
-    using pointer = const RegisterMaskPair *;
-    using reference = const RegisterMaskPair &;
+    using value_type = MCRegister;
+    using pointer = const MCRegister *;
+    using reference = const MCRegister &;
 
     liveout_iterator(const MachineBasicBlock &MBB, MCPhysReg ExceptionPointer,
                      MCPhysReg ExceptionSelector, bool End)
@@ -555,8 +531,7 @@ class MachineBasicBlock
         LiveRegI = (*BlockI)->livein_begin();
         if (!advanceToValidPosition())
           return;
-        if (LiveRegI->PhysReg == ExceptionPointer ||
-            LiveRegI->PhysReg == ExceptionSelector)
+        if (*LiveRegI == ExceptionPointer || *LiveRegI == ExceptionSelector)
           ++(*this);
       }
     }
@@ -566,9 +541,8 @@ class MachineBasicBlock
         ++LiveRegI;
         if (!advanceToValidPosition())
           return *this;
-      } while ((*BlockI)->isEHPad() &&
-               (LiveRegI->PhysReg == ExceptionPointer ||
-                LiveRegI->PhysReg == ExceptionSelector));
+      } while ((*BlockI)->isEHPad() && (*LiveRegI == ExceptionPointer ||
+                                        *LiveRegI == ExceptionSelector));
       return *this;
     }
 

llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp

@@ -153,7 +153,7 @@ void AggressiveAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
   // Examine the live-in regs of all successors.
   for (MachineBasicBlock *Succ : BB->successors())
     for (const auto &LI : Succ->liveins()) {
-      for (MCRegAliasIterator AI(LI.PhysReg, TRI, true); AI.isValid(); ++AI) {
+      for (MCRegAliasIterator AI(LI, TRI, true); AI.isValid(); ++AI) {
         unsigned Reg = *AI;
         State->UnionGroups(Reg, 0);
         KillIndices[Reg] = BB->size();

llvm/lib/CodeGen/BranchFolding.cpp

@@ -401,12 +401,7 @@ void BranchFolder::replaceTailWithBranchTo(MachineBasicBlock::iterator OldInst,
     // Merging the tails may have switched some undef operand to non-undef ones.
     // Add IMPLICIT_DEFS into OldMBB as necessary to have a definition of the
     // register.
-    for (MachineBasicBlock::RegisterMaskPair P : NewDest.liveins()) {
-      // We computed the liveins with computeLiveIn earlier and should only see
-      // full registers:
-      assert(P.LaneMask == LaneBitmask::getAll() &&
-             "Can only handle full register.");
-      MCRegister Reg = P.PhysReg;
+    for (MCRegister Reg : NewDest.liveins()) {
       if (!LiveRegs.available(*MRI, Reg))
         continue;
       DebugLoc DL;

llvm/lib/CodeGen/BranchRelaxation.cpp

@@ -582,11 +582,10 @@ bool BranchRelaxation::fixupUnconditionalBranch(MachineInstr &MI) {
 
     // Add live outs.
     for (const MachineBasicBlock *Succ : MBB->successors()) {
-      for (const MachineBasicBlock::RegisterMaskPair &LiveIn : Succ->liveins())
+      for (const MCRegister LiveIn : Succ->liveins())
         BranchBB->addLiveIn(LiveIn);
     }
 
-    BranchBB->sortUniqueLiveIns();
     BranchBB->addSuccessor(DestBB);
     MBB->replaceSuccessor(DestBB, BranchBB);
     if (TrampolineInsertionPoint == MBB)

llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp

@@ -66,10 +66,10 @@ void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
   // Examine the live-in regs of all successors.
   for (const MachineBasicBlock *Succ : BB->successors())
     for (const auto &LI : Succ->liveins()) {
-      for (MCRegAliasIterator AI(LI.PhysReg, TRI, true); AI.isValid(); ++AI) {
-        MCRegister Reg = *AI;
-        Classes[Reg.id()] = reinterpret_cast<TargetRegisterClass *>(-1);
-        KillIndices[Reg.id()] = BBSize;
+      for (MCRegAliasIterator AI(LI, TRI, true); AI.isValid(); ++AI) {
+        unsigned Reg = (*AI).id();
+        Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
+        KillIndices[Reg] = BBSize;
         DefIndices[Reg] = ~0u;
       }
     }

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

@@ -4181,9 +4181,8 @@ bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) {
                     EntryBB->end());
 
   // Update the live-in information for the new entry block.
-  for (const MachineBasicBlock::RegisterMaskPair &LiveIn : EntryBB->liveins())
+  for (const MCRegister LiveIn : EntryBB->liveins())
     NewEntryBB.addLiveIn(LiveIn);
-  NewEntryBB.sortUniqueLiveIns();
 
   // Get rid of the now empty basic block.
   EntryBB->removeSuccessor(&NewEntryBB);

llvm/lib/CodeGen/LiveIntervals.cpp

@@ -370,7 +370,7 @@ void LiveIntervals::computeLiveInRegUnits() {
     SlotIndex Begin = Indexes->getMBBStartIdx(&MBB);
     LLVM_DEBUG(dbgs() << Begin << "\t" << printMBBReference(MBB));
     for (const auto &LI : MBB.liveins()) {
-      for (MCRegUnit Unit : TRI->regunits(LI.PhysReg)) {
+      for (MCRegUnit Unit : TRI->regunits(LI)) {
         LiveRange *LR = RegUnitRanges[Unit];
         if (!LR) {
           // Use segment set to speed-up initial computation of the live range.

llvm/lib/CodeGen/LivePhysRegs.cpp

@@ -153,21 +153,8 @@ bool LivePhysRegs::available(const MachineRegisterInfo &MRI,
 
 /// Add live-in registers of basic block \p MBB to \p LiveRegs.
 void LivePhysRegs::addBlockLiveIns(const MachineBasicBlock &MBB) {
-  for (const auto &LI : MBB.liveins()) {
-    MCRegister Reg = LI.PhysReg;
-    LaneBitmask Mask = LI.LaneMask;
-    MCSubRegIndexIterator S(Reg, TRI);
-    assert(Mask.any() && "Invalid livein mask");
-    if (Mask.all() || !S.isValid()) {
-      addReg(Reg);
-      continue;
-    }
-    for (; S.isValid(); ++S) {
-      unsigned SI = S.getSubRegIndex();
-      if ((Mask & TRI->getSubRegIndexLaneMask(SI)).any())
-        addReg(S.getSubReg());
-    }
-  }
+  for (const MCRegister Reg : MBB.liveins())
+    addReg(Reg);
 }
 
 /// Adds all callee saved registers to \p LiveRegs.

llvm/lib/CodeGen/LiveRegUnits.cpp

@@ -88,7 +88,7 @@ void LiveRegUnits::accumulate(const MachineInstr &MI) {
 static void addBlockLiveIns(LiveRegUnits &LiveUnits,
                             const MachineBasicBlock &MBB) {
   for (const auto &LI : MBB.liveins())
-    LiveUnits.addRegMasked(LI.PhysReg, LI.LaneMask);
+    LiveUnits.addRegMasked(LI, LaneBitmask::getAll());
 }
 
 /// Adds all callee saved registers to \p LiveUnits.

llvm/lib/CodeGen/LiveVariables.cpp

@@ -570,9 +570,8 @@ void LiveVariables::runOnBlock(MachineBasicBlock *MBB, unsigned NumRegs) {
   // Mark live-in registers as live-in.
   SmallVector<Register, 4> Defs;
   for (const auto &LI : MBB->liveins()) {
-    assert(LI.PhysReg.isPhysical() &&
-           "Cannot have a live-in virtual register!");
-    HandlePhysRegDef(LI.PhysReg, nullptr, Defs);
+    assert(LI.isPhysical() && "Cannot have a live-in virtual register!");
+    HandlePhysRegDef(LI, nullptr, Defs);
   }
 
   // Loop over all of the instructions, processing them.
@@ -606,9 +605,9 @@ void LiveVariables::runOnBlock(MachineBasicBlock *MBB, unsigned NumRegs) {
     if (SuccMBB->isEHPad())
       continue;
     for (const auto &LI : SuccMBB->liveins()) {
-      if (!TRI->isInAllocatableClass(LI.PhysReg))
+      if (!TRI->isInAllocatableClass(LI))
         // Ignore other live-ins, e.g. those that are live into landing pads.
-        LiveOuts.insert(LI.PhysReg);
+        LiveOuts.insert(LI);
     }
   }
 

llvm/lib/CodeGen/MIRPrinter.cpp

@@ -769,13 +769,11 @@ void MIPrinter::print(const MachineBasicBlock &MBB) {
     const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
     OS.indent(2) << "liveins: ";
     bool First = true;
-    for (const auto &LI : MBB.liveins_dbg()) {
+    for (const Register Reg : MBB.liveins_dbg()) {
       if (!First)
         OS << ", ";
       First = false;
-      OS << printReg(LI.PhysReg, &TRI);
-      if (!LI.LaneMask.all())
-        OS << ":0x" << PrintLaneMask(LI.LaneMask);
+      OS << printReg(Reg, &TRI);
     }
     OS << "\n";
     HasLineAttributes = true;