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-42
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4 files changed

+59
-42
lines changed

‎llvm/include/llvm/CodeGen/TargetLowering.h

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -468,8 +468,10 @@ class TargetLoweringBase {
468468
return true;
469469
}
470470

471-
/// Return true if the @llvm.experimental.get.alias.lane.mask intrinsic should be expanded using generic code in SelectionDAGBuilder.
472-
virtual bool shouldExpandGetAliasLaneMask(EVT VT, EVT PtrVT, unsigned EltSize) const {
471+
/// Return true if the @llvm.experimental.get.alias.lane.mask intrinsic should
472+
/// be expanded using generic code in SelectionDAGBuilder.
473+
virtual bool shouldExpandGetAliasLaneMask(EVT VT, EVT PtrVT,
474+
unsigned EltSize) const {
473475
return true;
474476
}
475477

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 20 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -8288,42 +8288,48 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
82888288
SDValue SourceValue = getValue(I.getOperand(0));
82898289
SDValue SinkValue = getValue(I.getOperand(1));
82908290
SDValue EltSize = getValue(I.getOperand(2));
8291-
bool IsWriteAfterRead = cast<ConstantSDNode>(getValue(I.getOperand(3)))->getZExtValue() != 0;
8291+
bool IsWriteAfterRead =
8292+
cast<ConstantSDNode>(getValue(I.getOperand(3)))->getZExtValue() != 0;
82928293
auto IntrinsicVT = EVT::getEVT(I.getType());
82938294
auto PtrVT = SourceValue->getValueType(0);
82948295

8295-
if (!TLI.shouldExpandGetAliasLaneMask(IntrinsicVT, PtrVT, cast<ConstantSDNode>(EltSize)->getSExtValue())) {
8296+
if (!TLI.shouldExpandGetAliasLaneMask(
8297+
IntrinsicVT, PtrVT,
8298+
cast<ConstantSDNode>(EltSize)->getSExtValue())) {
82968299
visitTargetIntrinsic(I, Intrinsic);
82978300
return;
82988301
}
82998302

8300-
SDValue Diff = DAG.getNode(ISD::SUB, sdl,
8301-
PtrVT, SinkValue, SourceValue);
8303+
SDValue Diff = DAG.getNode(ISD::SUB, sdl, PtrVT, SinkValue, SourceValue);
83028304
if (!IsWriteAfterRead)
83038305
Diff = DAG.getNode(ISD::ABS, sdl, PtrVT, Diff);
83048306

83058307
Diff = DAG.getNode(ISD::SDIV, sdl, PtrVT, Diff, EltSize);
83068308
SDValue Zero = DAG.getTargetConstant(0, sdl, PtrVT);
83078309

83088310
// If the difference is positive then some elements may alias
8309-
auto CmpVT = TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
8310-
PtrVT);
8311-
SDValue Cmp = DAG.getSetCC(sdl, CmpVT, Diff, Zero, IsWriteAfterRead ? ISD::SETLE : ISD::SETEQ);
8311+
auto CmpVT =
8312+
TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), PtrVT);
8313+
SDValue Cmp = DAG.getSetCC(sdl, CmpVT, Diff, Zero,
8314+
IsWriteAfterRead ? ISD::SETLE : ISD::SETEQ);
83128315

83138316
// Splat the compare result then OR it with a lane mask
83148317
SDValue Splat = DAG.getSplat(IntrinsicVT, sdl, Cmp);
83158318

83168319
SDValue DiffMask;
83178320
// Don't emit an active lane mask if the target doesn't support it
83188321
if (TLI.shouldExpandGetActiveLaneMask(IntrinsicVT, PtrVT)) {
8319-
EVT VecTy = EVT::getVectorVT(*DAG.getContext(), PtrVT,
8320-
IntrinsicVT.getVectorElementCount());
8321-
SDValue DiffSplat = DAG.getSplat(VecTy, sdl, Diff);
8322-
SDValue VectorStep = DAG.getStepVector(sdl, VecTy);
8323-
DiffMask = DAG.getSetCC(sdl, IntrinsicVT, VectorStep,
8324-
DiffSplat, ISD::CondCode::SETULT);
8322+
EVT VecTy = EVT::getVectorVT(*DAG.getContext(), PtrVT,
8323+
IntrinsicVT.getVectorElementCount());
8324+
SDValue DiffSplat = DAG.getSplat(VecTy, sdl, Diff);
8325+
SDValue VectorStep = DAG.getStepVector(sdl, VecTy);
8326+
DiffMask = DAG.getSetCC(sdl, IntrinsicVT, VectorStep, DiffSplat,
8327+
ISD::CondCode::SETULT);
83258328
} else {
8326-
DiffMask = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, IntrinsicVT, DAG.getTargetConstant(Intrinsic::get_active_lane_mask, sdl, MVT::i64), Zero, Diff);
8329+
DiffMask = DAG.getNode(
8330+
ISD::INTRINSIC_WO_CHAIN, sdl, IntrinsicVT,
8331+
DAG.getTargetConstant(Intrinsic::get_active_lane_mask, sdl, MVT::i64),
8332+
Zero, Diff);
83278333
}
83288334
SDValue Or = DAG.getNode(ISD::OR, sdl, IntrinsicVT, DiffMask, Splat);
83298335
setValue(&I, Or);

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 33 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -2033,7 +2033,8 @@ bool AArch64TargetLowering::shouldExpandGetActiveLaneMask(EVT ResVT,
20332033
return false;
20342034
}
20352035

2036-
bool AArch64TargetLowering::shouldExpandGetAliasLaneMask(EVT VT, EVT PtrVT, unsigned EltSize) const {
2036+
bool AArch64TargetLowering::shouldExpandGetAliasLaneMask(
2037+
EVT VT, EVT PtrVT, unsigned EltSize) const {
20372038
if (!Subtarget->hasSVE2())
20382039
return true;
20392040

@@ -2042,7 +2043,7 @@ bool AArch64TargetLowering::shouldExpandGetAliasLaneMask(EVT VT, EVT PtrVT, unsi
20422043

20432044
if (VT == MVT::v2i1 || VT == MVT::nxv2i1)
20442045
return EltSize != 8;
2045-
if( VT == MVT::v4i1 || VT == MVT::nxv4i1)
2046+
if (VT == MVT::v4i1 || VT == MVT::nxv4i1)
20462047
return EltSize != 4;
20472048
if (VT == MVT::v8i1 || VT == MVT::nxv8i1)
20482049
return EltSize != 2;
@@ -5905,12 +5906,14 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
59055906
case Intrinsic::aarch64_sve_whilewr_h:
59065907
case Intrinsic::aarch64_sve_whilewr_s:
59075908
case Intrinsic::aarch64_sve_whilewr_d:
5908-
return DAG.getNode(AArch64ISD::WHILEWR, dl, Op.getValueType(), Op.getOperand(1), Op.getOperand(2));
5909+
return DAG.getNode(AArch64ISD::WHILEWR, dl, Op.getValueType(),
5910+
Op.getOperand(1), Op.getOperand(2));
59095911
case Intrinsic::aarch64_sve_whilerw_b:
59105912
case Intrinsic::aarch64_sve_whilerw_h:
59115913
case Intrinsic::aarch64_sve_whilerw_s:
59125914
case Intrinsic::aarch64_sve_whilerw_d:
5913-
return DAG.getNode(AArch64ISD::WHILERW, dl, Op.getValueType(), Op.getOperand(1), Op.getOperand(2));
5915+
return DAG.getNode(AArch64ISD::WHILERW, dl, Op.getValueType(),
5916+
Op.getOperand(1), Op.getOperand(2));
59145917
case Intrinsic::aarch64_neon_abs: {
59155918
EVT Ty = Op.getValueType();
59165919
if (Ty == MVT::i64) {
@@ -6377,34 +6380,38 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
63776380
uint64_t EltSize = Op.getOperand(3)->getAsZExtVal();
63786381
bool IsWriteAfterRead = Op.getOperand(4)->getAsZExtVal() == 1;
63796382
switch (EltSize) {
6380-
case 1:
6381-
IntrinsicID = IsWriteAfterRead ? Intrinsic::aarch64_sve_whilewr_b : Intrinsic::aarch64_sve_whilerw_b;
6382-
break;
6383-
case 2:
6384-
IntrinsicID = IsWriteAfterRead ? Intrinsic::aarch64_sve_whilewr_h : Intrinsic::aarch64_sve_whilerw_h;
6385-
break;
6386-
case 4:
6387-
IntrinsicID = IsWriteAfterRead ? Intrinsic::aarch64_sve_whilewr_s : Intrinsic::aarch64_sve_whilerw_s;
6388-
break;
6389-
case 8:
6390-
IntrinsicID = IsWriteAfterRead ? Intrinsic::aarch64_sve_whilewr_d : Intrinsic::aarch64_sve_whilerw_d;
6391-
break;
6392-
default:
6393-
llvm_unreachable("Unexpected element size for get.alias.lane.mask");
6394-
break;
6383+
case 1:
6384+
IntrinsicID = IsWriteAfterRead ? Intrinsic::aarch64_sve_whilewr_b
6385+
: Intrinsic::aarch64_sve_whilerw_b;
6386+
break;
6387+
case 2:
6388+
IntrinsicID = IsWriteAfterRead ? Intrinsic::aarch64_sve_whilewr_h
6389+
: Intrinsic::aarch64_sve_whilerw_h;
6390+
break;
6391+
case 4:
6392+
IntrinsicID = IsWriteAfterRead ? Intrinsic::aarch64_sve_whilewr_s
6393+
: Intrinsic::aarch64_sve_whilerw_s;
6394+
break;
6395+
case 8:
6396+
IntrinsicID = IsWriteAfterRead ? Intrinsic::aarch64_sve_whilewr_d
6397+
: Intrinsic::aarch64_sve_whilerw_d;
6398+
break;
6399+
default:
6400+
llvm_unreachable("Unexpected element size for get.alias.lane.mask");
6401+
break;
63956402
}
63966403
}
6397-
SDValue ID =
6398-
DAG.getTargetConstant(IntrinsicID, dl, MVT::i64);
6404+
SDValue ID = DAG.getTargetConstant(IntrinsicID, dl, MVT::i64);
63996405

64006406
EVT VT = Op.getValueType();
64016407
if (VT.isScalableVector())
64026408
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, ID, Op.getOperand(1),
64036409
Op.getOperand(2));
64046410

6405-
// We can use the SVE whilelo/whilewr/whilerw instruction to lower this intrinsic by
6406-
// creating the appropriate sequence of scalable vector operations and
6407-
// then extracting a fixed-width subvector from the scalable vector.
6411+
// We can use the SVE whilelo/whilewr/whilerw instruction to lower this
6412+
// intrinsic by creating the appropriate sequence of scalable vector
6413+
// operations and then extracting a fixed-width subvector from the scalable
6414+
// vector.
64086415

64096416
EVT ContainerVT = getContainerForFixedLengthVector(DAG, VT);
64106417
EVT WhileVT = ContainerVT.changeElementType(MVT::i1);
@@ -19544,7 +19551,8 @@ static bool isPredicateCCSettingOp(SDValue N) {
1954419551
// get_active_lane_mask is lowered to a whilelo instruction.
1954519552
N.getConstantOperandVal(0) == Intrinsic::get_active_lane_mask ||
1954619553
// get_alias_lane_mask is lowered to a whilewr/rw instruction.
19547-
N.getConstantOperandVal(0) == Intrinsic::experimental_get_alias_lane_mask)))
19554+
N.getConstantOperandVal(0) ==
19555+
Intrinsic::experimental_get_alias_lane_mask)))
1954819556
return true;
1954919557

1955019558
return false;

‎llvm/lib/Target/AArch64/AArch64ISelLowering.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -984,7 +984,8 @@ class AArch64TargetLowering : public TargetLowering {
984984

985985
bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const override;
986986

987-
bool shouldExpandGetAliasLaneMask(EVT VT, EVT PtrVT, unsigned EltSize) const override;
987+
bool shouldExpandGetAliasLaneMask(EVT VT, EVT PtrVT,
988+
unsigned EltSize) const override;
988989

989990
bool
990991
shouldExpandPartialReductionIntrinsic(const IntrinsicInst *I) const override;

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