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[MC][RISCV] Add assembly syntax highlighting for RISCV (#65853)
This patch adds support for syntax highlighting RISC-V assembly. Related patch: AArch64: https://reviews.llvm.org/D159162 X86: https://reviews.llvm.org/D159241
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-20
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‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

Lines changed: 47 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
1616
#include "llvm/MC/MCAsmInfo.h"
1717
#include "llvm/MC/MCExpr.h"
1818
#include "llvm/MC/MCInst.h"
19+
#include "llvm/MC/MCInstPrinter.h"
1920
#include "llvm/MC/MCRegisterInfo.h"
2021
#include "llvm/MC/MCSubtargetInfo.h"
2122
#include "llvm/MC/MCSymbol.h"
@@ -75,7 +76,7 @@ void RISCVInstPrinter::printInst(const MCInst *MI, uint64_t Address,
7576
}
7677

7778
void RISCVInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) const {
78-
O << getRegisterName(Reg);
79+
markup(O, Markup::Register) << getRegisterName(Reg);
7980
}
8081

8182
void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
@@ -90,7 +91,7 @@ void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
9091
}
9192

9293
if (MO.isImm()) {
93-
O << MO.getImm();
94+
markup(O, Markup::Immediate) << MO.getImm();
9495
return;
9596
}
9697

@@ -110,9 +111,9 @@ void RISCVInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address,
110111
uint64_t Target = Address + MO.getImm();
111112
if (!STI.hasFeature(RISCV::Feature64Bit))
112113
Target &= 0xffffffff;
113-
O << formatHex(Target);
114+
markup(O, Markup::Target) << formatHex(Target);
114115
} else {
115-
O << MO.getImm();
116+
markup(O, Markup::Target) << MO.getImm();
116117
}
117118
}
118119

@@ -123,11 +124,11 @@ void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo,
123124
auto SiFiveReg = RISCVSysReg::lookupSiFiveRegByEncoding(Imm);
124125
auto SysReg = RISCVSysReg::lookupSysRegByEncoding(Imm);
125126
if (SiFiveReg && SiFiveReg->haveVendorRequiredFeatures(STI.getFeatureBits()))
126-
O << SiFiveReg->Name;
127+
markup(O, Markup::Register) << SiFiveReg->Name;
127128
else if (SysReg && SysReg->haveRequiredFeatures(STI.getFeatureBits()))
128-
O << SysReg->Name;
129+
markup(O, Markup::Register) << SysReg->Name;
129130
else
130-
O << Imm;
131+
markup(O, Markup::Register) << Imm;
131132
}
132133

133134
void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo,
@@ -162,21 +163,21 @@ void RISCVInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNo,
162163
raw_ostream &O) {
163164
unsigned Imm = MI->getOperand(OpNo).getImm();
164165
if (Imm == 1) {
165-
O << "min";
166+
markup(O, Markup::Immediate) << "min";
166167
} else if (Imm == 30) {
167-
O << "inf";
168+
markup(O, Markup::Immediate) << "inf";
168169
} else if (Imm == 31) {
169-
O << "nan";
170+
markup(O, Markup::Immediate) << "nan";
170171
} else {
171172
float FPVal = RISCVLoadFPImm::getFPImm(Imm);
172173
// If the value is an integer, print a .0 fraction. Otherwise, use %g to
173174
// which will not print trailing zeros and will use scientific notation
174175
// if it is shorter than printing as a decimal. The smallest value requires
175176
// 12 digits of precision including the decimal.
176177
if (FPVal == (int)(FPVal))
177-
O << format("%.1f", FPVal);
178+
markup(O, Markup::Immediate) << format("%.1f", FPVal);
178179
else
179-
O << format("%.12g", FPVal);
180+
markup(O, Markup::Immediate) << format("%.12g", FPVal);
180181
}
181182
}
182183

@@ -211,16 +212,30 @@ void RISCVInstPrinter::printRlist(const MCInst *MI, unsigned OpNo,
211212
O << "{";
212213
switch (Imm) {
213214
case RISCVZC::RLISTENCODE::RA:
214-
O << (ArchRegNames ? "x1" : "ra");
215+
markup(O, Markup::Register) << (ArchRegNames ? "x1" : "ra");
215216
break;
216217
case RISCVZC::RLISTENCODE::RA_S0:
217-
O << (ArchRegNames ? "x1, x8" : "ra, s0");
218+
markup(O, Markup::Register) << (ArchRegNames ? "x1" : "ra");
219+
O << ", ";
220+
markup(O, Markup::Register) << (ArchRegNames ? "x8" : "s0");
218221
break;
219222
case RISCVZC::RLISTENCODE::RA_S0_S1:
220-
O << (ArchRegNames ? "x1, x8-x9" : "ra, s0-s1");
223+
markup(O, Markup::Register) << (ArchRegNames ? "x1" : "ra");
224+
O << ", ";
225+
markup(O, Markup::Register) << (ArchRegNames ? "x8" : "s0");
226+
O << '-';
227+
markup(O, Markup::Register) << (ArchRegNames ? "x9" : "s1");
221228
break;
222229
case RISCVZC::RLISTENCODE::RA_S0_S2:
223-
O << (ArchRegNames ? "x1, x8-x9, x18" : "ra, s0-s2");
230+
markup(O, Markup::Register) << (ArchRegNames ? "x1" : "ra");
231+
O << ", ";
232+
markup(O, Markup::Register) << (ArchRegNames ? "x8" : "s0");
233+
O << '-';
234+
markup(O, Markup::Register) << (ArchRegNames ? "x9" : "s2");
235+
if (ArchRegNames) {
236+
O << ", ";
237+
markup(O, Markup::Register) << "x18";
238+
}
224239
break;
225240
case RISCVZC::RLISTENCODE::RA_S0_S3:
226241
case RISCVZC::RLISTENCODE::RA_S0_S4:
@@ -229,11 +244,21 @@ void RISCVInstPrinter::printRlist(const MCInst *MI, unsigned OpNo,
229244
case RISCVZC::RLISTENCODE::RA_S0_S7:
230245
case RISCVZC::RLISTENCODE::RA_S0_S8:
231246
case RISCVZC::RLISTENCODE::RA_S0_S9:
232-
O << (ArchRegNames ? "x1, x8-x9, x18-" : "ra, s0-")
233-
<< getRegisterName(RISCV::X19 + (Imm - RISCVZC::RLISTENCODE::RA_S0_S3));
234-
break;
235247
case RISCVZC::RLISTENCODE::RA_S0_S11:
236-
O << (ArchRegNames ? "x1, x8-x9, x18-x27" : "ra, s0-s11");
248+
markup(O, Markup::Register) << (ArchRegNames ? "x1" : "ra");
249+
O << ", ";
250+
markup(O, Markup::Register) << (ArchRegNames ? "x8" : "s0");
251+
O << '-';
252+
if (ArchRegNames) {
253+
markup(O, Markup::Register) << "x9";
254+
O << ", ";
255+
markup(O, Markup::Register) << "x18";
256+
O << '-';
257+
}
258+
markup(O, Markup::Register) << getRegisterName(
259+
RISCV::X19 + (Imm == RISCVZC::RLISTENCODE::RA_S0_S11
260+
? 8
261+
: Imm - RISCVZC::RLISTENCODE::RA_S0_S3));
237262
break;
238263
default:
239264
llvm_unreachable("invalid register list");
@@ -256,6 +281,8 @@ void RISCVInstPrinter::printSpimm(const MCInst *MI, unsigned OpNo,
256281
if (Opcode == RISCV::CM_PUSH)
257282
Spimm = -Spimm;
258283

284+
// RAII guard for ANSI color escape sequences
285+
WithMarkup ScopedMarkup = markup(O, Markup::Immediate);
259286
RISCVZC::printSpimm(Spimm, O);
260287
}
261288

‎llvm/test/MC/Disassembler/RISCV/colored.txt

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,48 @@
1+
# UNSUPPORTED: system-windows
2+
# RUN: llvm-mc -triple=riscv64 -mattr=+zcmp,+experimental-zfa,+v --cdis %s | FileCheck %s --strict-whitespace --match-full-lines -check-prefixes=CHECK,ASM,ABINAME
3+
# RUN: llvm-mc -triple=riscv64 -mattr=+zcmp,+experimental-zfa,+v -M numeric --cdis %s | FileCheck %s --strict-whitespace --match-full-lines -check-prefixes=CHECK,ASM,ARCHNAME
4+
5+
# CHECK: .text
6+
# Registers and immediates
7+
0x03 0xe0 0x40 0x00
8+
# ABINAME-NEXT: lwu zero, 4(ra)
9+
# ARCHNAME-NEXT: lwu x0, 4(x1)
10+
11+
# Branch targets
12+
0x63 0x00 0xb5 0x04
13+
# ABINAME-NEXT: beq a0, a1, 64
14+
# ARCHNAME-NEXT: beq x10, x11, 64
15+
16+
# CSRs
17+
0xf3 0x23 0x10 0xf1
18+
# ABINAME-NEXT: csrr t2, mvendorid
19+
# ARCHNAME-NEXT: csrr x7, mvendorid
20+
21+
# FP immediates
22+
0xd3 0x00 0x1f 0xf0
23+
# ABINAME-NEXT: fli.s ft1, inf
24+
# ARCHNAME-NEXT: fli.s f1, inf
25+
0xd3 0x80 0x1e 0xf0
26+
# ABINAME-NEXT: fli.s ft1, 65536.0
27+
# ARCHNAME-NEXT: fli.s f1, 65536.0
28+
29+
# Rlist and spimm
30+
0x42 0xbe
31+
# ABINAME-NEXT: cm.popret {ra}, 16
32+
# ARCHNAME-NEXT: cm.popret {x1}, 16
33+
0x5e 0xbe
34+
# ABINAME-NEXT: cm.popret {ra, s0}, 64
35+
# ARCHNAME-NEXT: cm.popret {x1, x8}, 64
36+
0x62 0xbe
37+
# ABINAME-NEXT: cm.popret {ra, s0-s1}, 32
38+
# ARCHNAME-NEXT: cm.popret {x1, x8-x9}, 32
39+
0x76 0xbe
40+
# ABINAME-NEXT: cm.popret {ra, s0-s2}, 48
41+
# ARCHNAME-NEXT: cm.popret {x1, x8-x9, x18}, 48
42+
0xfe 0xbe
43+
# ABINAME-NEXT: cm.popret {ra, s0-s11}, 160
44+
# ARCHNAME-NEXT: cm.popret {x1, x8-x9, x18-x27}, 160
45+
46+
# mask registers
47+
0x57 0x04 0x4a 0x00
48+
# ASM-NEXT: vadd.vv v8, v4, v20, v0.t

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