[PreISelIntrinsicLowering][test] Test that the expanded memset.inline doesn't drop volatile flag

As suggested in the discussion for #98281.

Author: asb

llvm/test/Transforms/PreISelIntrinsicLowering/X86/memset-inline-non-constant-len.ll

@@ -27,8 +27,19 @@ define void @memset_x(ptr %a, i8 %value, i64 %x) nounwind {
 ; CHECK-NEXT:    [[TMP5:%.*]] = icmp ult i64 [[TMP4]], [[X]]
 ; CHECK-NEXT:    br i1 [[TMP5]], label %[[LOADSTORELOOP]], label %[[SPLIT]]
 ; CHECK:       [[SPLIT]]:
+; CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 0, [[X]]
+; CHECK-NEXT:    br i1 [[TMP6]], label %[[SPLIT1:.*]], label %[[LOADSTORELOOP2:.*]]
+; CHECK:       [[LOADSTORELOOP2]]:
+; CHECK-NEXT:    [[TMP7:%.*]] = phi i64 [ 0, %[[SPLIT]] ], [ [[TMP9:%.*]], %[[LOADSTORELOOP2]] ]
+; CHECK-NEXT:    [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[TMP7]]
+; CHECK-NEXT:    store volatile i8 [[VALUE]], ptr [[TMP8]], align 1
+; CHECK-NEXT:    [[TMP9]] = add i64 [[TMP7]], 1
+; CHECK-NEXT:    [[TMP10:%.*]] = icmp ult i64 [[TMP9]], [[X]]
+; CHECK-NEXT:    br i1 [[TMP10]], label %[[LOADSTORELOOP2]], label %[[SPLIT1]]
+; CHECK:       [[SPLIT1]]:
 ; CHECK-NEXT:    ret void
 ;
-  tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 %value, i64 %x, i1 0)
+  call void @llvm.memset.inline.p0.i64(ptr %a, i8 %value, i64 %x, i1 0)
+  tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 %value, i64 %x, i1 1)
   ret void
 }