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Kai Luo
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[PowerPC] Support huge frame size for PPC64
Support allocation of huge stack frame(>2g) on PPC64. For ELFv2 ABI on Linux, quoted from the spec 2.2.3.1 General Stack Frame Requirements > There is no maximum stack frame size defined. On AIX, XL allows such huge frame. Reviewed By: #powerpc, nemanjai Differential Revision: https://reviews.llvm.org/D107886
1 parent eaf48dd commit 5018a5d

10 files changed

+270
-91
lines changed

‎llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

Lines changed: 5 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -626,7 +626,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
626626
// Work out frame sizes.
627627
uint64_t FrameSize = determineFrameLayoutAndUpdate(MF);
628628
int64_t NegFrameSize = -FrameSize;
629-
if (!isInt<32>(FrameSize) || !isInt<32>(NegFrameSize))
629+
if (!isPPC64 && (!isInt<32>(FrameSize) || !isInt<32>(NegFrameSize)))
630630
llvm_unreachable("Unhandled stack size!");
631631

632632
if (MFI.isFrameAddressTaken())
@@ -661,10 +661,6 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
661661
: PPC::STWU );
662662
const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
663663
: PPC::STWUX);
664-
const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
665-
: PPC::LIS );
666-
const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
667-
: PPC::ORI );
668664
const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
669665
: PPC::OR );
670666
const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
@@ -935,11 +931,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
935931
.addImm(NegFrameSize);
936932
} else {
937933
assert(!SingleScratchReg && "Only a single scratch reg available");
938-
BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg)
939-
.addImm(NegFrameSize >> 16);
940-
BuildMI(MBB, MBBI, dl, OrImmInst, TempReg)
941-
.addReg(TempReg, RegState::Kill)
942-
.addImm(NegFrameSize & 0xFFFF);
934+
TII.materializeImmPostRA(MBB, MBBI, dl, TempReg, NegFrameSize);
943935
BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg)
944936
.addReg(ScratchReg, RegState::Kill)
945937
.addReg(TempReg, RegState::Kill);
@@ -958,11 +950,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
958950
.addReg(SPReg);
959951

960952
} else {
961-
BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
962-
.addImm(NegFrameSize >> 16);
963-
BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
964-
.addReg(ScratchReg, RegState::Kill)
965-
.addImm(NegFrameSize & 0xFFFF);
953+
TII.materializeImmPostRA(MBB, MBBI, dl, ScratchReg, NegFrameSize);
966954
BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
967955
.addReg(SPReg, RegState::Kill)
968956
.addReg(SPReg)
@@ -1669,7 +1657,7 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
16691657
// values from the stack, and set SPAdd to the value that needs to be added
16701658
// to the SP at the end. The default values are as if red zone was present.
16711659
unsigned RBReg = SPReg;
1672-
unsigned SPAdd = 0;
1660+
uint64_t SPAdd = 0;
16731661

16741662
// Check if we can move the stack update instruction up the epilogue
16751663
// past the callee saves. This will allow the move to LR instruction
@@ -1727,11 +1715,7 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
17271715
BuildMI(MBB, MBBI, dl, AddImmInst, RBReg)
17281716
.addReg(FPReg).addImm(FrameSize);
17291717
} else {
1730-
BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1731-
.addImm(FrameSize >> 16);
1732-
BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1733-
.addReg(ScratchReg, RegState::Kill)
1734-
.addImm(FrameSize & 0xFFFF);
1718+
TII.materializeImmPostRA(MBB, MBBI, dl, ScratchReg, FrameSize);
17351719
BuildMI(MBB, MBBI, dl, AddInst)
17361720
.addReg(RBReg)
17371721
.addReg(FPReg)

‎llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -189,7 +189,7 @@ namespace {
189189
}
190190

191191
/// getSmallIPtrImm - Return a target constant of pointer type.
192-
inline SDValue getSmallIPtrImm(unsigned Imm, const SDLoc &dl) {
192+
inline SDValue getSmallIPtrImm(uint64_t Imm, const SDLoc &dl) {
193193
return CurDAG->getTargetConstant(
194194
Imm, dl, PPCLowering->getPointerTy(CurDAG->getDataLayout()));
195195
}
@@ -203,7 +203,7 @@ namespace {
203203
/// base register. Return the virtual register that holds this value.
204204
SDNode *getGlobalBaseReg();
205205

206-
void selectFrameIndex(SDNode *SN, SDNode *N, unsigned Offset = 0);
206+
void selectFrameIndex(SDNode *SN, SDNode *N, uint64_t Offset = 0);
207207

208208
// Select - Convert the specified operand from a target-independent to a
209209
// target-specific node if it hasn't already been changed.
@@ -640,7 +640,7 @@ static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
640640
&& isInt32Immediate(N->getOperand(1).getNode(), Imm);
641641
}
642642

643-
void PPCDAGToDAGISel::selectFrameIndex(SDNode *SN, SDNode *N, unsigned Offset) {
643+
void PPCDAGToDAGISel::selectFrameIndex(SDNode *SN, SDNode *N, uint64_t Offset) {
644644
SDLoc dl(SN);
645645
int FI = cast<FrameIndexSDNode>(N)->getIndex();
646646
SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
@@ -5379,7 +5379,7 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
53795379
// If this is equivalent to an add, then we can fold it with the
53805380
// FrameIndex calculation.
53815381
if ((LHSKnown.Zero.getZExtValue()|~(uint64_t)Imm) == ~0ULL) {
5382-
selectFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
5382+
selectFrameIndex(N, N->getOperand(0).getNode(), (int64_t)Imm);
53835383
return;
53845384
}
53855385
}
@@ -5437,7 +5437,7 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
54375437
int16_t Imm;
54385438
if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
54395439
isIntS16Immediate(N->getOperand(1), Imm)) {
5440-
selectFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
5440+
selectFrameIndex(N, N->getOperand(0).getNode(), (int64_t)Imm);
54415441
return;
54425442
}
54435443

‎llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3234,6 +3234,47 @@ MachineInstr *PPCInstrInfo::getDefMIPostRA(unsigned Reg, MachineInstr &MI,
32343234
return nullptr;
32353235
}
32363236

3237+
void PPCInstrInfo::materializeImmPostRA(MachineBasicBlock &MBB,
3238+
MachineBasicBlock::iterator MBBI,
3239+
const DebugLoc &DL, Register Reg,
3240+
int64_t Imm) const {
3241+
assert(!MBB.getParent()->getRegInfo().isSSA() &&
3242+
"Register should be in non-SSA form after RA");
3243+
bool isPPC64 = Subtarget.isPPC64();
3244+
// FIXME: Materialization here is not optimal.
3245+
// For some special bit patterns we can use less instructions.
3246+
// See `selectI64ImmDirect` in PPCISelDAGToDAG.cpp.
3247+
if (isInt<16>(Imm)) {
3248+
BuildMI(MBB, MBBI, DL, get(isPPC64 ? PPC::LI8 : PPC::LI), Reg).addImm(Imm);
3249+
} else if (isInt<32>(Imm)) {
3250+
BuildMI(MBB, MBBI, DL, get(isPPC64 ? PPC::LIS8 : PPC::LIS), Reg)
3251+
.addImm(Imm >> 16);
3252+
if (Imm & 0xFFFF)
3253+
BuildMI(MBB, MBBI, DL, get(isPPC64 ? PPC::ORI8 : PPC::ORI), Reg)
3254+
.addReg(Reg, RegState::Kill)
3255+
.addImm(Imm & 0xFFFF);
3256+
} else {
3257+
assert(isPPC64 && "Materializing 64-bit immediate to single register is "
3258+
"only supported in PPC64");
3259+
BuildMI(MBB, MBBI, DL, get(PPC::LIS8), Reg).addImm(Imm >> 48);
3260+
if ((Imm >> 32) & 0xFFFF)
3261+
BuildMI(MBB, MBBI, DL, get(PPC::ORI8), Reg)
3262+
.addReg(Reg, RegState::Kill)
3263+
.addImm((Imm >> 32) & 0xFFFF);
3264+
BuildMI(MBB, MBBI, DL, get(PPC::RLDICR), Reg)
3265+
.addReg(Reg, RegState::Kill)
3266+
.addImm(32)
3267+
.addImm(31);
3268+
BuildMI(MBB, MBBI, DL, get(PPC::ORIS8), Reg)
3269+
.addReg(Reg, RegState::Kill)
3270+
.addImm((Imm >> 16) & 0xFFFF);
3271+
if (Imm & 0xFFFF)
3272+
BuildMI(MBB, MBBI, DL, get(PPC::ORI8), Reg)
3273+
.addReg(Reg, RegState::Kill)
3274+
.addImm(Imm & 0xFFFF);
3275+
}
3276+
}
3277+
32373278
MachineInstr *PPCInstrInfo::getForwardingDefMI(
32383279
MachineInstr &MI,
32393280
unsigned &OpNoForForwarding,

‎llvm/lib/Target/PowerPC/PPCInstrInfo.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -746,6 +746,12 @@ class PPCInstrInfo : public PPCGenInstrInfo {
746746
MachineInstr *getDefMIPostRA(unsigned Reg, MachineInstr &MI,
747747
bool &SeenIntermediateUse) const;
748748

749+
// Materialize immediate after RA.
750+
void materializeImmPostRA(MachineBasicBlock &MBB,
751+
MachineBasicBlock::iterator MBBI,
752+
const DebugLoc &DL, Register Reg,
753+
int64_t Imm) const;
754+
749755
/// getRegNumForOperand - some operands use different numbering schemes
750756
/// for the same registers. For example, a VSX instruction may have any of
751757
/// vs0-vs63 allocated whereas an Altivec instruction could only have

‎llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1477,7 +1477,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
14771477
OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC);
14781478

14791479
// Now add the frame object offset to the offset from r1.
1480-
int Offset = MFI.getObjectOffset(FrameIndex);
1480+
int64_t Offset = MFI.getObjectOffset(FrameIndex);
14811481
Offset += MI.getOperand(OffsetOperandNo).getImm();
14821482

14831483
// If we're not using a Frame Pointer that has been set to the value of the
@@ -1537,13 +1537,16 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
15371537
// Insert a set of rA with the full offset value before the ld, st, or add
15381538
if (isInt<16>(Offset))
15391539
BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg)
1540-
.addImm(Offset);
1541-
else {
1540+
.addImm(Offset);
1541+
else if (isInt<32>(Offset)) {
15421542
BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
1543-
.addImm(Offset >> 16);
1543+
.addImm(Offset >> 16);
15441544
BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
1545-
.addReg(SRegHi, RegState::Kill)
1546-
.addImm(Offset);
1545+
.addReg(SRegHi, RegState::Kill)
1546+
.addImm(Offset);
1547+
} else {
1548+
assert(is64Bit && "Huge stack is only supported on PPC64");
1549+
TII.materializeImmPostRA(MBB, II, dl, SReg, Offset);
15471550
}
15481551

15491552
// Convert into indexed form of the instruction:

‎llvm/test/CodeGen/PowerPC/huge-frame-call.ll

Lines changed: 121 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,121 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-linux-gnu < %s \
3+
; RUN: 2>&1 | FileCheck --check-prefix=CHECK-LE %s
4+
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff < %s \
5+
; RUN: 2>&1 | FileCheck --check-prefix=CHECK-BE %s
6+
7+
%0 = type <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, [8 x i8] }>
8+
@global.1 = internal global %0 <{ i32 129, i32 2, i32 118, i32 0, i32 5, i32 0, i32 0, i32 0, i32 120, i32 0, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @global.2, i32 0, i32 0), [8 x i8] c"\00\00\00\00\00\00\00\03" }>, align 4
9+
@global.2 = internal constant [3 x i8] c"x.c"
10+
@alias = dso_local alias i32 (), i32 ()* @main
11+
12+
define dso_local signext i32 @main() nounwind {
13+
; CHECK-LE-LABEL: main:
14+
; CHECK-LE: # %bb.0: # %bb
15+
; CHECK-LE-NEXT: mflr 0
16+
; CHECK-LE-NEXT: std 0, 16(1)
17+
; CHECK-LE-NEXT: lis 0, -1
18+
; CHECK-LE-NEXT: ori 0, 0, 65535
19+
; CHECK-LE-NEXT: sldi 0, 0, 32
20+
; CHECK-LE-NEXT: oris 0, 0, 32767
21+
; CHECK-LE-NEXT: ori 0, 0, 65120
22+
; CHECK-LE-NEXT: stdux 1, 1, 0
23+
; CHECK-LE-NEXT: lis 3, 0
24+
; CHECK-LE-NEXT: sldi 3, 3, 32
25+
; CHECK-LE-NEXT: oris 3, 3, 32768
26+
; CHECK-LE-NEXT: ori 3, 3, 400
27+
; CHECK-LE-NEXT: stdx 30, 1, 3 # 8-byte Folded Spill
28+
; CHECK-LE-NEXT: bl pluto
29+
; CHECK-LE-NEXT: nop
30+
; CHECK-LE-NEXT: addis 3, 2, global.1@toc@ha
31+
; CHECK-LE-NEXT: li 4, 0
32+
; CHECK-LE-NEXT: li 7, 0
33+
; CHECK-LE-NEXT: li 8, 0
34+
; CHECK-LE-NEXT: li 9, 0
35+
; CHECK-LE-NEXT: addi 5, 3, global.1@toc@l
36+
; CHECK-LE-NEXT: ori 6, 4, 32768
37+
; CHECK-LE-NEXT: li 3, 6
38+
; CHECK-LE-NEXT: li 4, 257
39+
; CHECK-LE-NEXT: bl snork
40+
; CHECK-LE-NEXT: nop
41+
; CHECK-LE-NEXT: mr 30, 3
42+
; CHECK-LE-NEXT: li 3, 344
43+
; CHECK-LE-NEXT: addi 4, 1, 48
44+
; CHECK-LE-NEXT: li 5, 8
45+
; CHECK-LE-NEXT: li 6, 8
46+
; CHECK-LE-NEXT: oris 3, 3, 32768
47+
; CHECK-LE-NEXT: add 4, 4, 3
48+
; CHECK-LE-NEXT: mr 3, 30
49+
; CHECK-LE-NEXT: bl zot
50+
; CHECK-LE-NEXT: nop
51+
; CHECK-LE-NEXT: mr 3, 30
52+
; CHECK-LE-NEXT: bl wibble
53+
; CHECK-LE-NEXT: nop
54+
; CHECK-LE-NEXT: li 3, 0
55+
; CHECK-LE-NEXT: bl snork.3
56+
; CHECK-LE-NEXT: nop
57+
;
58+
; CHECK-BE-LABEL: main:
59+
; CHECK-BE: # %bb.0: # %bb
60+
; CHECK-BE-NEXT: mflr 0
61+
; CHECK-BE-NEXT: std 0, 16(1)
62+
; CHECK-BE-NEXT: lis 0, -1
63+
; CHECK-BE-NEXT: ori 0, 0, 65535
64+
; CHECK-BE-NEXT: sldi 0, 0, 32
65+
; CHECK-BE-NEXT: oris 0, 0, 32767
66+
; CHECK-BE-NEXT: ori 0, 0, 65056
67+
; CHECK-BE-NEXT: stdux 1, 1, 0
68+
; CHECK-BE-NEXT: lis 3, 0
69+
; CHECK-BE-NEXT: sldi 3, 3, 32
70+
; CHECK-BE-NEXT: oris 3, 3, 32768
71+
; CHECK-BE-NEXT: ori 3, 3, 472
72+
; CHECK-BE-NEXT: stdx 31, 1, 3 # 8-byte Folded Spill
73+
; CHECK-BE-NEXT: bl .pluto[PR]
74+
; CHECK-BE-NEXT: nop
75+
; CHECK-BE-NEXT: ld 5, L..C0(2) # @global.1
76+
; CHECK-BE-NEXT: li 3, 0
77+
; CHECK-BE-NEXT: ori 6, 3, 32768
78+
; CHECK-BE-NEXT: li 3, 6
79+
; CHECK-BE-NEXT: li 4, 257
80+
; CHECK-BE-NEXT: li 7, 0
81+
; CHECK-BE-NEXT: li 8, 0
82+
; CHECK-BE-NEXT: li 9, 0
83+
; CHECK-BE-NEXT: bl .snork[PR]
84+
; CHECK-BE-NEXT: nop
85+
; CHECK-BE-NEXT: mr 31, 3
86+
; CHECK-BE-NEXT: li 3, 344
87+
; CHECK-BE-NEXT: oris 3, 3, 32768
88+
; CHECK-BE-NEXT: addi 4, 1, 120
89+
; CHECK-BE-NEXT: add 4, 4, 3
90+
; CHECK-BE-NEXT: mr 3, 31
91+
; CHECK-BE-NEXT: li 5, 8
92+
; CHECK-BE-NEXT: li 6, 8
93+
; CHECK-BE-NEXT: bl .zot[PR]
94+
; CHECK-BE-NEXT: nop
95+
; CHECK-BE-NEXT: mr 3, 31
96+
; CHECK-BE-NEXT: bl .wibble[PR]
97+
; CHECK-BE-NEXT: nop
98+
; CHECK-BE-NEXT: li 3, 0
99+
; CHECK-BE-NEXT: bl .snork.3[PR]
100+
; CHECK-BE-NEXT: nop
101+
bb:
102+
%tmp = alloca [2147484000 x i8], align 8
103+
tail call void @pluto()
104+
%tmp6 = tail call i64 @snork(i64 6, i32 257, %0* nonnull @global.1, i64 32768, i8* null, i64 0, i8* null)
105+
%tmp7 = getelementptr inbounds [2147484000 x i8], [2147484000 x i8]* %tmp, i64 0, i64 2147483992
106+
%tmp8 = bitcast i8* %tmp7 to double*
107+
%tmp9 = call i64 @zot(i64 %tmp6, double* nonnull %tmp8, i64 8, i64 8)
108+
%tmp10 = call i64 @wibble(i64 %tmp6)
109+
call void @snork.3(i64 0)
110+
unreachable
111+
}
112+
113+
declare void @pluto()
114+
115+
declare signext i64 @snork(i64, i32, %0*, i64, i8*, i64, i8*)
116+
117+
declare signext i64 @zot(i64, double*, i64, i64)
118+
119+
declare signext i64 @wibble(i64)
120+
121+
declare void @snork.3(i64)

‎llvm/test/CodeGen/PowerPC/huge-frame-size.ll

Lines changed: 45 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,17 +1,57 @@
1-
; REQUIRES: asserts
2-
; RUN: not --crash llc -verify-machineinstrs -mtriple=powerpc64le-linux-gnu < %s \
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-linux-gnu < %s \
33
; RUN: 2>&1 | FileCheck --check-prefix=CHECK-LE %s
4-
; RUN: not --crash llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff < %s \
4+
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff < %s \
55
; RUN: 2>&1 | FileCheck --check-prefix=CHECK-BE %s
66

77
declare void @bar(i8*)
88

99
define void @foo(i8 %x) {
10-
; CHECK-LE: Unhandled stack size
11-
; CHECK-BE: Unhandled stack size
10+
; CHECK-LE-LABEL: foo:
11+
; CHECK-LE: # %bb.0: # %entry
12+
; CHECK-LE-NEXT: lis 0, -1
13+
; CHECK-LE-NEXT: ori 0, 0, 65534
14+
; CHECK-LE-NEXT: sldi 0, 0, 32
15+
; CHECK-LE-NEXT: oris 0, 0, 65535
16+
; CHECK-LE-NEXT: ori 0, 0, 65504
17+
; CHECK-LE-NEXT: stdux 1, 1, 0
18+
; CHECK-LE-NEXT: .cfi_def_cfa_offset 32
19+
; CHECK-LE-NEXT: li 4, 1
20+
; CHECK-LE-NEXT: li 5, -1
21+
; CHECK-LE-NEXT: addi 6, 1, 32
22+
; CHECK-LE-NEXT: stb 3, 32(1)
23+
; CHECK-LE-NEXT: rldic 4, 4, 31, 32
24+
; CHECK-LE-NEXT: rldic 5, 5, 0, 32
25+
; CHECK-LE-NEXT: stbx 3, 6, 4
26+
; CHECK-LE-NEXT: stbx 3, 6, 5
27+
; CHECK-LE-NEXT: ld 1, 0(1)
28+
; CHECK-LE-NEXT: blr
29+
;
30+
; CHECK-BE-LABEL: foo:
31+
; CHECK-BE: # %bb.0: # %entry
32+
; CHECK-BE-NEXT: lis 0, -1
33+
; CHECK-BE-NEXT: ori 0, 0, 65534
34+
; CHECK-BE-NEXT: sldi 0, 0, 32
35+
; CHECK-BE-NEXT: oris 0, 0, 65535
36+
; CHECK-BE-NEXT: ori 0, 0, 65488
37+
; CHECK-BE-NEXT: stdux 1, 1, 0
38+
; CHECK-BE-NEXT: li 4, 1
39+
; CHECK-BE-NEXT: addi 5, 1, 48
40+
; CHECK-BE-NEXT: rldic 4, 4, 31, 32
41+
; CHECK-BE-NEXT: stb 3, 48(1)
42+
; CHECK-BE-NEXT: stbx 3, 5, 4
43+
; CHECK-BE-NEXT: li 4, -1
44+
; CHECK-BE-NEXT: rldic 4, 4, 0, 32
45+
; CHECK-BE-NEXT: stbx 3, 5, 4
46+
; CHECK-BE-NEXT: ld 1, 0(1)
47+
; CHECK-BE-NEXT: blr
1248
entry:
1349
%a = alloca i8, i64 4294967296, align 16
1450
%b = getelementptr i8, i8* %a, i64 0
51+
%c = getelementptr i8, i8* %a, i64 2147483648
52+
%d = getelementptr i8, i8* %a, i64 4294967295
1553
store volatile i8 %x, i8* %b
54+
store volatile i8 %x, i8* %c
55+
store volatile i8 %x, i8* %d
1656
ret void
1757
}

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