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[RISCV] Add Qualcomm uC Xqcilia (Large Immediate Arithmetic) extension (#124706)
This extension adds eight 48 bit large arithmetic instructions. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support.
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‎clang/test/Driver/print-supported-extensions-riscv.c

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@@ -200,6 +200,7 @@
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// CHECK-NEXT: xqcics 0.2 'Xqcics' (Qualcomm uC Conditional Select Extension)
201201
// CHECK-NEXT: xqcicsr 0.2 'Xqcicsr' (Qualcomm uC CSR Extension)
202202
// CHECK-NEXT: xqciint 0.2 'Xqciint' (Qualcomm uC Interrupts Extension)
203+
// CHECK-NEXT: xqcilia 0.2 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
203204
// CHECK-NEXT: xqcilo 0.2 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
204205
// CHECK-NEXT: xqcilsm 0.2 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
205206
// CHECK-NEXT: xqcisls 0.2 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)

‎llvm/docs/RISCVUsage.rst

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@@ -450,6 +450,9 @@ The current vendor extensions supported are:
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``experimental-Xqciint``
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LLVM implements `version 0.2 of the Qualcomm uC Interrupts extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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``experimental-Xqcilia``
454+
LLVM implements `version 0.2 of the Qualcomm uC Large Immediate Arithmetic extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
455+
453456
``experimental-Xqcilo``
454457
LLVM implements `version 0.2 of the Qualcomm uC Large Offset Load Store extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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‎llvm/docs/ReleaseNotes.md

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@@ -107,6 +107,9 @@ Changes to the PowerPC Backend
107107
Changes to the RISC-V Backend
108108
-----------------------------
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* Adds experimental assembler support for the Qualcomm uC 'Xqcilia` (Large Immediate Arithmetic)
111+
extension.
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110113
Changes to the WebAssembly Backend
111114
----------------------------------
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‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

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Original file line numberDiff line numberDiff line change
@@ -1056,6 +1056,16 @@ struct RISCVOperand final : public MCParsedAsmOperand {
10561056
isInt<26>(fixImmediateForRV32(Imm, isRV64Imm()));
10571057
}
10581058

1059+
bool isSImm32() const {
1060+
int64_t Imm;
1061+
RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
1062+
if (!isImm())
1063+
return false;
1064+
bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
1065+
return IsConstantImm && isInt<32>(fixImmediateForRV32(Imm, isRV64Imm())) &&
1066+
VK == RISCVMCExpr::VK_RISCV_None;
1067+
}
1068+
10591069
/// getStartLoc - Gets location of the first token of this operand
10601070
SMLoc getStartLoc() const override { return StartLoc; }
10611071
/// getEndLoc - Gets location of the last token of this operand
@@ -1665,6 +1675,10 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
16651675
case Match_InvalidSImm26:
16661676
return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 25),
16671677
(1 << 25) - 1);
1678+
case Match_InvalidSImm32:
1679+
return generateImmOutOfRangeError(Operands, ErrorInfo,
1680+
std::numeric_limits<int32_t>::min(),
1681+
std::numeric_limits<uint32_t>::max());
16681682
case Match_InvalidRnumArg: {
16691683
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 10);
16701684
}

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

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@@ -767,6 +767,8 @@ DecodeStatus RISCVDisassembler::getInstruction48(MCInst &MI, uint64_t &Size,
767767
for (size_t i = Size; i-- != 0;) {
768768
Insn += (static_cast<uint64_t>(Bytes[i]) << 8 * i);
769769
}
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TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcilia, DecoderTableXqcilia48,
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"Qualcomm uC Large Immediate Arithmetic 48bit");
770772
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcilo, DecoderTableXqcilo48,
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"Qualcomm uC Large Offset Load Store 48bit");
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‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

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@@ -327,6 +327,7 @@ enum OperandType : unsigned {
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OPERAND_SIMM12,
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OPERAND_SIMM12_LSB00000,
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OPERAND_SIMM26,
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OPERAND_SIMM32,
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OPERAND_CLUI_IMM,
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OPERAND_VTYPEI10,
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OPERAND_VTYPEI11,

‎llvm/lib/Target/RISCV/RISCVFeatures.td

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@@ -1358,6 +1358,14 @@ def HasVendorXqciint
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AssemblerPredicate<(all_of FeatureVendorXqciint),
13591359
"'Xqciint' (Qualcomm uC Interrupts Extension)">;
13601360

1361+
def FeatureVendorXqcilia
1362+
: RISCVExperimentalExtension<0, 2, "Qualcomm uC Large Immediate Arithmetic Extension",
1363+
[FeatureStdExtZca]>;
1364+
def HasVendorXqcilia
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: Predicate<"Subtarget->hasVendorXqcilia()">,
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AssemblerPredicate<(all_of FeatureVendorXqcilia),
1367+
"'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)">;
1368+
13611369
def FeatureVendorXqcilo
13621370
: RISCVExperimentalExtension<0, 2, "Qualcomm uC Large Offset Load Store Extension",
13631371
[FeatureStdExtZca]>;

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td

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@@ -34,6 +34,21 @@ def uimm11 : RISCVUImmLeafOp<11>;
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3535
def simm26 : RISCVSImmLeafOp<26>;
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37+
// 32-bit Immediate, used by RV32 Instructions in 32-bit operations, so no
38+
// sign-/zero-extension. This is represented internally as a signed 32-bit value.
39+
def simm32 : RISCVOp<XLenVT> {
40+
let ParserMatchClass = SImmAsmOperand<32, "">;
41+
let EncoderMethod = "getImmOpValue";
42+
let DecoderMethod = "decodeSImmOperand<32>";
43+
let OperandType = "OPERAND_SIMM32";
44+
let MCOperandPredicate = [{
45+
int64_t Imm;
46+
if (MCOp.evaluateAsConstantImm(Imm))
47+
return isInt<32>(Imm);
48+
return false;
49+
}];
50+
}
51+
3752
//===----------------------------------------------------------------------===//
3853
// Instruction Formats
3954
//===----------------------------------------------------------------------===//
@@ -245,6 +260,25 @@ class QCIRVInstESStore<bits<3> funct3, bits<2> funct2, string opcodestr>
245260
(ins GPRMem:$rs2, GPR:$rs1, simm26:$imm),
246261
opcodestr, "$rs2, ${imm}(${rs1})">;
247262

263+
class QCIRVInstEAI<bits<3> funct3, bits<1> funct1, string opcodestr>
264+
: RVInst48<(outs GPRNoX0:$rd_wb), (ins GPRNoX0:$rd, simm32:$imm),
265+
opcodestr, "$rd, $imm", [], InstFormatOther> {
266+
bits<5> rd;
267+
bits<32> imm;
268+
269+
let Constraints = "$rd = $rd_wb";
270+
let Inst{47-16} = imm{31-0};
271+
let Inst{15} = funct1;
272+
let Inst{14-12} = funct3;
273+
let Inst{11-7} = rd;
274+
let Inst{6-0} = 0b0011111;
275+
}
276+
277+
class QCIRVInstEI<bits<3> funct3, bits<2> funct2, string opcodestr>
278+
: QCIRVInstEIBase<funct3, funct2, (outs GPRNoX0:$rd),
279+
(ins GPRNoX0:$rs1, simm26:$imm), opcodestr,
280+
"$rd, $rs1, $imm">;
281+
248282
//===----------------------------------------------------------------------===//
249283
// Instructions
250284
//===----------------------------------------------------------------------===//
@@ -435,6 +469,20 @@ let Predicates = [HasVendorXqcilo, IsRV32], DecoderNamespace = "Xqcilo" in {
435469
def QC_E_SW : QCIRVInstESStore<0b110, 0b11, "qc.e.sw">;
436470
} // Predicates = [HasVendorXqcilo, IsRV32], DecoderNamespace = "Xqcilo"
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472+
let Predicates = [HasVendorXqcilia, IsRV32], DecoderNamespace = "Xqcilia" in {
473+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
474+
def QC_E_XORAI : QCIRVInstEAI<0b001, 0b0, "qc.e.xorai">;
475+
def QC_E_ORAI : QCIRVInstEAI<0b001, 0b1, "qc.e.orai" >;
476+
def QC_E_ADDAI : QCIRVInstEAI<0b010, 0b0, "qc.e.addai">;
477+
def QC_E_ANDAI : QCIRVInstEAI<0b010, 0b1, "qc.e.andai">;
478+
479+
def QC_E_XORI : QCIRVInstEI<0b011, 0b00, "qc.e.xori">;
480+
def QC_E_ORI : QCIRVInstEI<0b011, 0b01, "qc.e.ori" >;
481+
def QC_E_ADDI : QCIRVInstEI<0b011, 0b10, "qc.e.addi">;
482+
def QC_E_ANDI : QCIRVInstEI<0b011, 0b11, "qc.e.andi">;
483+
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
484+
} // Predicates = [HasVendorXqcilia, IsRV32], DecoderNamespace = "Xqcilia"
485+
438486
//===----------------------------------------------------------------------===//
439487
// Aliases
440488
//===----------------------------------------------------------------------===//

‎llvm/lib/TargetParser/RISCVISAInfo.cpp

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@@ -742,8 +742,9 @@ Error RISCVISAInfo::checkDependency() {
742742
bool HasZvl = MinVLen != 0;
743743
bool HasZcmt = Exts.count("zcmt") != 0;
744744
static constexpr StringLiteral XqciExts[] = {
745-
{"xqcia"}, {"xqciac"}, {"xqcicli"}, {"xqcicm"}, {"xqcics"},
746-
{"xqcicsr"}, {"xqciint"}, {"xqcilo"}, {"xqcilsm"}, {"xqcisls"}};
745+
{"xqcia"}, {"xqciac"}, {"xqcicli"}, {"xqcicm"},
746+
{"xqcics"}, {"xqcicsr"}, {"xqciint"}, {"xqcilia"},
747+
{"xqcilo"}, {"xqcilsm"}, {"xqcisls"}};
747748

748749
if (HasI && HasE)
749750
return getIncompatibleError("i", "e");

‎llvm/test/CodeGen/RISCV/attributes.ll

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@@ -88,6 +88,7 @@
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics %s -o - | FileCheck --check-prefix=RV32XQCICS %s
8989
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicsr %s -o - | FileCheck --check-prefix=RV32XQCICSR %s
9090
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqciint %s -o - | FileCheck --check-prefix=RV32XQCIINT %s
91+
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilia %s -o - | FileCheck --check-prefix=RV32XQCILIA %s
9192
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilo %s -o - | FileCheck --check-prefix=RV32XQCILO %s
9293
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilsm %s -o - | FileCheck --check-prefix=RV32XQCILSM %s
9394
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisls %s -o - | FileCheck --check-prefix=RV32XQCISLS %s
@@ -404,6 +405,7 @@
404405
; RV32XQCICS: .attribute 5, "rv32i2p1_xqcics0p2"
405406
; RV32XQCICSR: .attribute 5, "rv32i2p1_xqcicsr0p2"
406407
; RV32XQCIINT: .attribute 5, "rv32i2p1_zca1p0_xqciint0p2"
408+
; RV32XQCILIA: .attribute 5, "rv32i2p1_zca1p0_xqcilia0p2"
407409
; RV32XQCILO: .attribute 5, "rv32i2p1_zca1p0_xqcilo0p2"
408410
; RV32XQCILSM: .attribute 5, "rv32i2p1_xqcilsm0p2"
409411
; RV32XQCISLS: .attribute 5, "rv32i2p1_xqcisls0p2"

‎llvm/test/MC/RISCV/xqcilia-invalid.s

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@@ -0,0 +1,117 @@
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# Xqcilia - Qualcomm uC Large Immediate Arithmetic extension
2+
# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcilia < %s 2>&1 \
3+
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS,CHECK-IMM %s
4+
# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcilia < %s 2>&1 \
5+
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS,CHECK-EXT %s
6+
7+
# CHECK-PLUS: :[[@LINE+2]]:12: error: register must be a GPR excluding zero (x0)
8+
# CHECK-MINUS: :[[@LINE+1]]:12: error: invalid operand for instruction
9+
qc.e.addai 9, 33554432
10+
11+
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
12+
qc.e.addai x9
13+
14+
# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 4294967295]
15+
qc.e.addai x9, 20485546494
16+
17+
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
18+
qc.e.addai x9, 33554432
19+
20+
21+
# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero (x0)
22+
# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction
23+
qc.e.addi x10, 9, 554432
24+
25+
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
26+
qc.e.addi x10, x9
27+
28+
# CHECK-IMM: :[[@LINE+1]]:20: error: immediate must be an integer in the range [-33554432, 33554431]
29+
qc.e.addi x10, x9, 335544312
30+
31+
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
32+
qc.e.addi x10, x9, 554432
33+
34+
35+
# CHECK-PLUS: :[[@LINE+2]]:12: error: register must be a GPR excluding zero (x0)
36+
# CHECK-MINUS: :[[@LINE+1]]:12: error: invalid operand for instruction
37+
qc.e.andai 9, 33554432
38+
39+
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
40+
qc.e.andai x9
41+
42+
# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 4294967295]
43+
qc.e.andai x9, 20494437494
44+
45+
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
46+
qc.e.andai x9, 33554432
47+
48+
49+
# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero (x0)
50+
# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction
51+
qc.e.andi x10, 9, 554432
52+
53+
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
54+
qc.e.andi x10, x9
55+
56+
# CHECK-IMM: :[[@LINE+1]]:20: error: immediate must be an integer in the range [-33554432, 33554431]
57+
qc.e.andi x10, x9, 335544312
58+
59+
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
60+
qc.e.andi x10, x9, 554432
61+
62+
63+
# CHECK-PLUS: :[[@LINE+2]]:11: error: register must be a GPR excluding zero (x0)
64+
# CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction
65+
qc.e.orai 9, 33554432
66+
67+
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
68+
qc.e.orai x9
69+
70+
# CHECK-IMM: :[[@LINE+1]]:15: error: immediate must be an integer in the range [-2147483648, 4294967295]
71+
qc.e.orai x9, 20494437494
72+
73+
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
74+
qc.e.orai x9, 33554432
75+
76+
77+
# CHECK-PLUS: :[[@LINE+2]]:15: error: register must be a GPR excluding zero (x0)
78+
# CHECK-MINUS: :[[@LINE+1]]:15: error: invalid operand for instruction
79+
qc.e.ori x10, 9, 554432
80+
81+
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
82+
qc.e.ori x10, x9
83+
84+
# CHECK-IMM: :[[@LINE+1]]:19: error: immediate must be an integer in the range [-33554432, 33554431]
85+
qc.e.ori x10, x9, 335544312
86+
87+
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
88+
qc.e.ori x10, x9, 554432
89+
90+
91+
92+
# CHECK-PLUS: :[[@LINE+2]]:12: error: register must be a GPR excluding zero (x0)
93+
# CHECK-MINUS: :[[@LINE+1]]:12: error: invalid operand for instruction
94+
qc.e.xorai 9, 33554432
95+
96+
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
97+
qc.e.xorai x9
98+
99+
# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 4294967295]
100+
qc.e.xorai x9, 20494437494
101+
102+
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
103+
qc.e.xorai x9, 33554432
104+
105+
106+
# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero (x0)
107+
# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction
108+
qc.e.xori x10, 9, 554432
109+
110+
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
111+
qc.e.xori x10, x9
112+
113+
# CHECK-IMM: :[[@LINE+1]]:20: error: immediate must be an integer in the range [-33554432, 33554431]
114+
qc.e.xori x10, x9, 335544312
115+
116+
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
117+
qc.e.xori x10, x9, 554432

‎llvm/test/MC/RISCV/xqcilia-valid.s

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@@ -0,0 +1,82 @@
1+
# Xqcilia - Qualcomm uC Large Immediate Arithmetic extension
2+
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilia -riscv-no-aliases -show-encoding \
3+
# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
4+
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilia < %s \
5+
# RUN: | llvm-objdump --mattr=+experimental-xqcilia -M no-aliases --no-print-imm-hex -d - \
6+
# RUN: | FileCheck -check-prefix=CHECK-INST %s
7+
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilia -show-encoding \
8+
# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
9+
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilia < %s \
10+
# RUN: | llvm-objdump --mattr=+experimental-xqcilia --no-print-imm-hex -d - \
11+
# RUN: | FileCheck -check-prefix=CHECK-INST %s
12+
13+
# CHECK-INST: qc.e.addai s1, -1
14+
# CHECK-ENC: encoding: [0x9f,0x24,0xff,0xff,0xff,0xff]
15+
qc.e.addai x9, 4294967295
16+
17+
# CHECK-INST: qc.e.addai s1, -2147483648
18+
# CHECK-ENC: encoding: [0x9f,0x24,0x00,0x00,0x00,0x80]
19+
qc.e.addai x9, -2147483648
20+
21+
22+
# CHECK-INST: qc.e.addi a0, s1, -33554432
23+
# CHECK-ENC: encoding: [0x1f,0xb5,0x04,0x80,0x00,0x80]
24+
qc.e.addi x10, x9, -33554432
25+
26+
# CHECK-INST: qc.e.addi a0, s1, 33554431
27+
# CHECK-ENC: encoding: [0x1f,0xb5,0xf4,0xbf,0xff,0x7f]
28+
qc.e.addi x10, x9, 33554431
29+
30+
31+
# CHECK-INST: qc.e.andai s1, -1
32+
# CHECK-ENC: encoding: [0x9f,0xa4,0xff,0xff,0xff,0xff]
33+
qc.e.andai x9, 4294967295
34+
35+
# CHECK-INST: qc.e.andai s1, -2147483648
36+
# CHECK-ENC: encoding: [0x9f,0xa4,0x00,0x00,0x00,0x80]
37+
qc.e.andai x9, -2147483648
38+
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# CHECK-INST: qc.e.andi a0, s1, -33554432
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# CHECK-ENC: encoding: [0x1f,0xb5,0x04,0xc0,0x00,0x80]
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qc.e.andi x10, x9, -33554432
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# CHECK-INST: qc.e.andi a0, s1, 33554431
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# CHECK-ENC: encoding: [0x1f,0xb5,0xf4,0xff,0xff,0x7f]
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qc.e.andi x10, x9, 33554431
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# CHECK-INST: qc.e.orai s1, -1
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# CHECK-ENC: encoding: [0x9f,0x94,0xff,0xff,0xff,0xff]
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qc.e.orai x9, 4294967295
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# CHECK-INST: qc.e.orai s1, -2147483648
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# CHECK-ENC: encoding: [0x9f,0x94,0x00,0x00,0x00,0x80]
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qc.e.orai x9, -2147483648
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# CHECK-INST: qc.e.ori a0, s1, -33554432
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# CHECK-ENC: encoding: [0x1f,0xb5,0x04,0x40,0x00,0x80]
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qc.e.ori x10, x9, -33554432
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# CHECK-INST: qc.e.ori a0, s1, 33554431
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# CHECK-ENC: encoding: [0x1f,0xb5,0xf4,0x7f,0xff,0x7f]
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qc.e.ori x10, x9, 33554431
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# CHECK-INST: qc.e.xorai s1, -1
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# CHECK-ENC: encoding: [0x9f,0x14,0xff,0xff,0xff,0xff]
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qc.e.xorai x9, 4294967295
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# CHECK-INST: qc.e.xorai s1, -2147483648
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# CHECK-ENC: encoding: [0x9f,0x14,0x00,0x00,0x00,0x80]
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qc.e.xorai x9, -2147483648
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# CHECK-INST: qc.e.xori a0, s1, -33554432
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# CHECK-ENC: encoding: [0x1f,0xb5,0x04,0x00,0x00,0x80]
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qc.e.xori x10, x9, -33554432
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# CHECK-INST: qc.e.xori a0, s1, 33554431
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# CHECK-ENC: encoding: [0x1f,0xb5,0xf4,0x3f,0xff,0x7f]
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qc.e.xori x10, x9, 33554431

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