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[AMDGPU][True16][CodeGen] update VGPRimm for t16 (#131021)
added a `bitcast_fpimm_to_i16` and update the VGPRImm pattern for t16 flow. This change is following the pattern from the 32bit case
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llvm/lib/Target/AMDGPU/SIInstrInfo.td

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@@ -846,6 +846,11 @@ def cond_as_i32imm: SDNodeXForm<cond, [{
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}]>;
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// Copied from the AArch64 backend:
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def bitcast_fpimm_to_i16 : SDNodeXForm<fpimm, [{
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return CurDAG->getTargetConstant(
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N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i16);
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}]>;
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def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
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return CurDAG->getTargetConstant(
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N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);

llvm/lib/Target/AMDGPU/SIInstructions.td

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@@ -2308,7 +2308,7 @@ let True16Predicate = UseRealTrue16Insts in {
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foreach vt = [f16, bf16] in {
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def : GCNPat <
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(VGPRImm<(vt fpimm)>:$imm),
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(V_MOV_B16_t16_e64 0, $imm, 0)
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(V_MOV_B16_t16_e64 0, (vt (bitcast_fpimm_to_i16 $imm)), 0)
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>;
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}
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}

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