Skip to content

Commit 54f5e02

Browse files
pravinjagtaparsenm
pravinjagtap
authored and
arsenm
committed
AMDGPU: Increase the LDS size to support to 160 KB for gfx950
1 parent 1eebc85 commit 54f5e02

File tree

10 files changed

+144
-5
lines changed

10 files changed

+144
-5
lines changed

‎llvm/docs/AMDGPUUsage.rst

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5475,6 +5475,8 @@ The fields used by CP for code objects before V3 also match those specified in
54755475
roundup(lds-size / (64 * 4))
54765476
GFX7-GFX11
54775477
roundup(lds-size / (128 * 4))
5478+
GFX950
5479+
roundup(lds-size / (320 * 4))
54785480

54795481
24 1 bit ENABLE_EXCEPTION_IEEE_754_FP Wavefront starts execution
54805482
_INVALID_OPERATION with specified exceptions

‎llvm/lib/Target/AMDGPU/AMDGPU.td

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1494,7 +1494,8 @@ def FeatureISAVersion9_5_Common : FeatureSet<
14941494
[FeatureFP8Insts,
14951495
FeatureFP8ConversionInsts,
14961496
FeatureCvtFP8VOP1Bug,
1497-
FeatureGFX950Insts
1497+
FeatureGFX950Insts,
1498+
FeatureAddressableLocalMemorySize163840
14981499
])>;
14991500

15001501
def FeatureISAVersion9_4_0 : FeatureSet<

‎llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1172,12 +1172,16 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
11721172
ProgInfo.DX10Clamp = Mode.DX10Clamp;
11731173

11741174
unsigned LDSAlignShift;
1175-
if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
1176-
// LDS is allocated in 64 dword blocks.
1177-
LDSAlignShift = 8;
1178-
} else {
1175+
if (STM.getFeatureBits().test(FeatureAddressableLocalMemorySize163840)) {
1176+
// LDS is allocated in 320 dword blocks.
1177+
LDSAlignShift = 11;
1178+
} else if (STM.getFeatureBits().test(
1179+
FeatureAddressableLocalMemorySize65536)) {
11791180
// LDS is allocated in 128 dword blocks.
11801181
LDSAlignShift = 9;
1182+
} else {
1183+
// LDS is allocated in 64 dword blocks.
1184+
LDSAlignShift = 8;
11811185
}
11821186

11831187
ProgInfo.SGPRSpill = MFI->getNumSpilledSGPRs();

‎llvm/lib/Target/AMDGPU/AMDGPUFeatures.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@ class SubtargetFeatureAddressableLocalMemorySize <int Value> : SubtargetFeature<
2929

3030
def FeatureAddressableLocalMemorySize32768 : SubtargetFeatureAddressableLocalMemorySize<32768>;
3131
def FeatureAddressableLocalMemorySize65536 : SubtargetFeatureAddressableLocalMemorySize<65536>;
32+
def FeatureAddressableLocalMemorySize163840 : SubtargetFeatureAddressableLocalMemorySize<163840>;
3233

3334
class SubtargetFeatureWavefrontSize <int ValueLog2> : SubtargetFeature<
3435
"wavefrontsize"#!shl(1, ValueLog2),

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -916,6 +916,8 @@ unsigned getAddressableLocalMemorySize(const MCSubtargetInfo *STI) {
916916
return 32768;
917917
if (STI->getFeatureBits().test(FeatureAddressableLocalMemorySize65536))
918918
return 65536;
919+
if (STI->getFeatureBits().test(FeatureAddressableLocalMemorySize163840))
920+
return 163840;
919921
return 0;
920922
}
921923

‎llvm/test/CodeGen/AMDGPU/extra-lds-size.ll

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,8 @@
22
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10-MESA %s
33
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11-PAL %s
44
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11-MESA %s
5+
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx950 < %s | FileCheck -check-prefix=GFX950-PAL %s
6+
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx950 < %s | FileCheck -check-prefix=GFX950-MESA %s
57
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX1200-PAL %s
68
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX1200-MESA %s
79

@@ -17,6 +19,11 @@
1719
; GFX11-MESA: .long 45100
1820
; GFX11-MESA-NEXT: .long 1024
1921

22+
; GFX950-PAL: '0x2c0b (SPI_SHADER_PGM_RSRC2_PS)': 0x200
23+
24+
; GFX950-MESA: .long 45100
25+
; GFX950-MESA-NEXT: .long 512
26+
2027
; GFX1200-PAL: '0x2c0b (SPI_SHADER_PGM_RSRC2_PS)': 0x400
2128

2229
; GFX1200-MESA: .long 45100

‎llvm/test/CodeGen/AMDGPU/lds-limit-diagnostics-gfx950.ll

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,13 @@
1+
; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR %s
2+
3+
; GFX950 supports upto 160 KB LDS memory.
4+
; This is a negative test to check when the LDS size exceeds the max usable limit.
5+
6+
; ERROR: error: <unknown>:0:0: local memory (163844) exceeds limit (163840) in function 'test_lds_limit'
7+
@dst = addrspace(3) global [40961 x i32] poison
8+
9+
define amdgpu_kernel void @test_lds_limit(i32 %val) {
10+
%gep = getelementptr [40961 x i32], ptr addrspace(3) @dst, i32 0, i32 100
11+
store i32 %val, ptr addrspace(3) %gep
12+
ret void
13+
}

‎llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx950.ll

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,31 @@
1+
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
2+
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx950 -verify-machineinstrs < %s | FileCheck -check-prefix=MESA %s
3+
4+
; gfx950 supports upto 160 KB configurable LDS memory.
5+
; This test checks the max and above the old i.e. 128 KiB size of LDS that can be allocated.
6+
7+
@lds.i32 = addrspace(3) global i32 poison
8+
@lds.array.size.131076 = addrspace(3) global [32768 x i32] poison
9+
@lds.array.size.163840 = addrspace(3) global [40959 x i32] poison
10+
11+
; GCN-LABEL: test_lds_array_size_131076:
12+
; GCN: .amdhsa_group_segment_fixed_size 131076
13+
; GCN: ; LDSByteSize: 131076 bytes/workgroup
14+
; MESA: granulated_lds_size = 65
15+
define amdgpu_kernel void @test_lds_array_size_131076() {
16+
%gep = getelementptr inbounds [32768 x i32], ptr addrspace(3) @lds.array.size.131076, i32 0, i32 20
17+
%val = load i32, ptr addrspace(3) %gep
18+
store i32 %val, ptr addrspace(3) @lds.i32
19+
ret void
20+
}
21+
22+
; GCN-LABEL: test_lds_array_size_163840:
23+
; GCN: .amdhsa_group_segment_fixed_size 163840
24+
; GCN: ; LDSByteSize: 163840 bytes/workgroup
25+
; MESA: granulated_lds_size = 80
26+
define amdgpu_kernel void @test_lds_array_size_163840() {
27+
%gep = getelementptr inbounds [40959 x i32], ptr addrspace(3) @lds.array.size.163840 , i32 0, i32 20
28+
%val = load i32, ptr addrspace(3) %gep
29+
store i32 %val, ptr addrspace(3) @lds.i32
30+
ret void
31+
}

‎llvm/test/CodeGen/AMDGPU/lds-size-pal-gfx950.ll

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx950 -verify-machineinstrs < %s | FileCheck -check-prefix=PAL %s
2+
3+
; GFX950supports upto 160 KB configurable LDS memory.
4+
; This test checks the min and max size of LDS that can be allocated.
5+
6+
; PAL: .shader_functions:
7+
; PAL: test_lds_array_i32:
8+
; PAL: .lds_size: 0x28000
9+
; PAL: test_lds_i32:
10+
; PAL: .lds_size: 0x4
11+
12+
13+
@lds.i32 = addrspace(3) global i32 poison
14+
@lds.array.i32 = addrspace(3) global [40959 x i32] poison
15+
16+
define amdgpu_gfx void @test_lds_i32(i32 %val) {
17+
store i32 %val, ptr addrspace(3) @lds.i32
18+
ret void
19+
}
20+
21+
define amdgpu_gfx void @test_lds_array_i32() {
22+
%gep = getelementptr inbounds [40959 x i32], ptr addrspace(3) @lds.array.i32, i32 0, i32 20
23+
%val = load i32, ptr addrspace(3) %gep
24+
store i32 %val, ptr addrspace(3) @lds.i32
25+
ret void
26+
}

‎llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx950.s

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,52 @@
1+
;; Test disassembly for gfx950 kernel descriptor.
2+
3+
; RUN: rm -rf %t && split-file %s %t && cd %t
4+
5+
;--- 1.s
6+
; RUN: llvm-mc --triple=amdgcn-amd-amdhsa -mattr=-xnack -filetype=obj -mcpu=gfx950 < 1.s > 1.o
7+
; RUN: llvm-objdump --disassemble-symbols=kernel.kd 1.o | tail -n +7 | tee 1-disasm.s | FileCheck 1.s
8+
; RUN: llvm-mc --triple=amdgcn-amd-amdhsa -mattr=-xnack -filetype=obj -mcpu=gfx950 < 1-disasm.s > 1-disasm.o
9+
; FIxMe: cmp 1.o 1-disasm.o
10+
; CHECK: .amdhsa_kernel kernel
11+
; CHECK-NEXT: .amdhsa_group_segment_fixed_size 163840
12+
; CHECK-NEXT: .amdhsa_private_segment_fixed_size 0
13+
; CHECK-NEXT: .amdhsa_kernarg_size 0
14+
; CHECK-NEXT: .amdhsa_accum_offset 4
15+
; CHECK-NEXT: .amdhsa_tg_split 0
16+
; CHECK-NEXT: .amdhsa_next_free_vgpr 8
17+
; CHECK-NEXT: .amdhsa_reserve_vcc 0
18+
; CHECK-NEXT: .amdhsa_reserve_xnack_mask 0
19+
; CHECK-NEXT: .amdhsa_next_free_sgpr 8
20+
; CHECK-NEXT: .amdhsa_float_round_mode_32 0
21+
; CHECK-NEXT: .amdhsa_float_round_mode_16_64 0
22+
; CHECK-NEXT: .amdhsa_float_denorm_mode_32 0
23+
; CHECK-NEXT: .amdhsa_float_denorm_mode_16_64 3
24+
; CHECK-NEXT: .amdhsa_dx10_clamp 1
25+
; CHECK-NEXT: .amdhsa_ieee_mode 1
26+
; CHECK-NEXT: .amdhsa_fp16_overflow 0
27+
; CHECK-NEXT: .amdhsa_enable_private_segment 0
28+
; CHECK-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1
29+
; CHECK-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0
30+
; CHECK-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0
31+
; CHECK-NEXT: .amdhsa_system_sgpr_workgroup_info 0
32+
; CHECK-NEXT: .amdhsa_system_vgpr_workitem_id 0
33+
; CHECK-NEXT: .amdhsa_exception_fp_ieee_invalid_op 0
34+
; CHECK-NEXT: .amdhsa_exception_fp_denorm_src 0
35+
; CHECK-NEXT: .amdhsa_exception_fp_ieee_div_zero 0
36+
; CHECK-NEXT: .amdhsa_exception_fp_ieee_overflow 0
37+
; CHECK-NEXT: .amdhsa_exception_fp_ieee_underflow 0
38+
; CHECK-NEXT: .amdhsa_exception_fp_ieee_inexact 0
39+
; CHECK-NEXT: .amdhsa_exception_int_div_zero 0
40+
; CHECK-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
41+
; CHECK-NEXT: .amdhsa_user_sgpr_queue_ptr 0
42+
; CHECK-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0
43+
; CHECK-NEXT: .amdhsa_user_sgpr_dispatch_id 0
44+
; CHECK-NEXT: .amdhsa_user_sgpr_private_segment_size 0
45+
; CHECK-NEXT: .amdhsa_uses_dynamic_stack 0
46+
; CHECK-NEXT:.end_amdhsa_kernel
47+
.amdhsa_kernel kernel
48+
.amdhsa_group_segment_fixed_size 163840
49+
.amdhsa_next_free_vgpr 0
50+
.amdhsa_next_free_sgpr 0
51+
.amdhsa_accum_offset 4
52+
.end_amdhsa_kernel

0 commit comments

Comments
 (0)