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[LV] Fix stale entry in MinBWs in tryToWiden
tryToWiden attempts to replace an Instruction with a Constant from SCEV, but forgets to erase the Instruction from the MinBWs map, leading to a crash in VPlanTransforms::truncateToMinimalBitwidths. Fix this by erasing the stale entry. Fixes #125278.
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+28
-8
lines changed

2 files changed

+28
-8
lines changed

llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1047,9 +1047,7 @@ class LoopVectorizationCostModel {
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/// \returns The smallest bitwidth each instruction can be represented with.
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/// The vector equivalents of these instructions should be truncated to this
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/// type.
1050-
const MapVector<Instruction *, uint64_t> &getMinimalBitwidths() const {
1051-
return MinBWs;
1052-
}
1050+
MapVector<Instruction *, uint64_t> &getMinimalBitwidths() { return MinBWs; }
10531051

10541052
/// \returns True if it is more profitable to scalarize instruction \p I for
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/// vectorization factor \p VF.
@@ -8868,12 +8866,15 @@ VPWidenRecipe *VPRecipeBuilder::tryToWiden(Instruction *I,
88688866
auto GetConstantViaSCEV = [this, &SE](VPValue *Op) {
88698867
if (!Op->isLiveIn())
88708868
return Op;
8871-
Value *V = Op->getUnderlyingValue();
8872-
if (isa<Constant>(V) || !SE.isSCEVable(V->getType()))
8869+
Instruction *I = dyn_cast<Instruction>(Op->getLiveInIRValue());
8870+
if (!I || !SE.isSCEVable(I->getType()))
88738871
return Op;
8874-
auto *C = dyn_cast<SCEVConstant>(SE.getSCEV(V));
8872+
auto *C = dyn_cast<SCEVConstant>(SE.getSCEV(I));
88758873
if (!C)
88768874
return Op;
8875+
// If we're going to replace an instruction with a constant, erase any
8876+
// stale entry in MinBWs.
8877+
CM.getMinimalBitwidths().erase(I);
88778878
return Plan.getOrAddLiveIn(C->getValue());
88788879
};
88798880
// For Mul, the legacy cost model checks both operands.

llvm/test/Transforms/LoopVectorize/pr125278.ll

Lines changed: 21 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,26 @@
1-
; REQUIRES: asserts
2-
; RUN: not --crash opt -passes=loop-vectorize -disable-output %s
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2+
; RUN: opt -passes=loop-vectorize -S %s | FileCheck %s
33

44
define void @pr125278(ptr %dst, i64 %n) {
5+
; CHECK-LABEL: define void @pr125278(
6+
; CHECK-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) {
7+
; CHECK-NEXT: [[ENTRY:.*:]]
8+
; CHECK-NEXT: [[TRUE_EXT:%.*]] = zext i1 true to i32
9+
; CHECK-NEXT: br label %[[COND:.*]]
10+
; CHECK: [[COND_LOOPEXIT:.*]]:
11+
; CHECK-NEXT: br label %[[COND]]
12+
; CHECK: [[COND]]:
13+
; CHECK-NEXT: br label %[[LOOP:.*]]
14+
; CHECK: [[LOOP]]:
15+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[COND]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
16+
; CHECK-NEXT: [[FALSE_EXT:%.*]] = zext i1 false to i32
17+
; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[FALSE_EXT]], [[TRUE_EXT]]
18+
; CHECK-NEXT: [[XOR_TRUNC:%.*]] = trunc i32 [[XOR]] to i8
19+
; CHECK-NEXT: store i8 [[XOR_TRUNC]], ptr [[DST]], align 1
20+
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
21+
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[IV_NEXT]], [[N]]
22+
; CHECK-NEXT: br i1 [[CMP]], label %[[LOOP]], label %[[COND_LOOPEXIT]]
23+
;
524
entry:
625
%true.ext = zext i1 true to i32
726
br label %cond

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