Skip to content

Commit 55fc5eb

Browse files
committed
[LV] Add additional cost model tests with inductions and truncates.
Add test coverage for additional cases not covered by current tests with multiple inductions and truncates.
1 parent ce763bf commit 55fc5eb

File tree

2 files changed

+184
-0
lines changed

2 files changed

+184
-0
lines changed

llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll

Lines changed: 73 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -213,6 +213,79 @@ exit:
213213
ret void
214214
}
215215

216+
define void @multiple_pointer_ivs_with_scalar_uses_only(ptr %A, ptr %B) #0 {
217+
entry:
218+
br label %loop
219+
220+
loop:
221+
%iv.1 = phi i32 [ 100, %entry ], [ %dec, %loop ]
222+
%iv.2 = phi i32 [ 2048, %entry ], [ %add38, %loop ]
223+
%ptr.iv.1 = phi ptr [ %A, %entry ], [ %outptr.0, %loop ]
224+
%ptr.iv.2 = phi ptr [ %B, %entry ], [ %incdec.ptr36, %loop ]
225+
%ptr.iv.3 = phi ptr [ %B, %entry ], [ %incdec.ptr33, %loop ]
226+
%incdec.ptr33 = getelementptr i8, ptr %ptr.iv.3, i64 1
227+
%0 = load i8, ptr %ptr.iv.3, align 1
228+
%conv34 = zext i8 %0 to i32
229+
%incdec.ptr36 = getelementptr i8, ptr %ptr.iv.2, i64 1
230+
%1 = load i8, ptr %ptr.iv.2, align 1
231+
%conv37 = zext i8 %1 to i32
232+
%add38 = add i32 %conv34, %conv37
233+
%shr42 = lshr i32 %iv.2, 1
234+
%conv43 = trunc i32 %shr42 to i8
235+
store i8 %conv43, ptr %ptr.iv.1, align 1
236+
%dec = add i32 %iv.1, 1
237+
%outptr.0 = getelementptr i8, ptr %ptr.iv.1, i64 2
238+
%cmp30.not = icmp eq i32 %dec, 0
239+
br i1 %cmp30.not, label %exit, label %loop
240+
241+
exit:
242+
ret void
243+
}
244+
245+
define i16 @iv_and_step_trunc() {
246+
entry:
247+
br label %loop
248+
249+
loop:
250+
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
251+
%rec = phi i16 [ 0, %entry ], [ %rec.next, %loop ]
252+
%iv.next = add i64 %iv, 1
253+
%0 = trunc i64 %iv to i16
254+
%1 = trunc i64 %iv.next to i16
255+
%rec.next = mul i16 %0, %1
256+
%ec = icmp eq i64 %iv, 1
257+
br i1 %ec, label %exit, label %loop
258+
259+
exit:
260+
ret i16 %rec
261+
}
262+
263+
define i32 @test_scalar_predicated_cost(i64 %x, i64 %y, ptr %A) #0 {
264+
entry:
265+
br label %loop.header
266+
267+
loop.header:
268+
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]
269+
%cmp9.not = icmp ule i64 %iv, %y
270+
br i1 %cmp9.not, label %loop.latch, label %if.then
271+
272+
if.then:
273+
%or = or i64 %x, %iv
274+
%gep = getelementptr i32, ptr %A, i64 %iv
275+
%t = trunc i64 %or to i32
276+
store i32 %t, ptr %gep, align 4
277+
br label %loop.latch
278+
279+
loop.latch:
280+
%iv.next = add i64 %iv, 1
281+
%ec = icmp eq i64 %iv, 100
282+
br i1 %ec, label %exit, label %loop.header
283+
284+
exit:
285+
ret i32 0
286+
}
287+
288+
216289
attributes #0 = { "min-legal-vector-width"="0" "target-cpu"="skylake-avx512" }
217290
;.
218291
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
Lines changed: 111 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,111 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
2+
; RUN: opt -p loop-vectorize -mtriple=x86_64-apple-macosx -S %s | FileCheck %s
3+
4+
target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
5+
6+
define i32 @test_scalar_predicated_cost(i64 %x, i64 %y, ptr %A) #0 {
7+
; CHECK-LABEL: define i32 @test_scalar_predicated_cost(
8+
; CHECK-SAME: i64 [[X:%.*]], i64 [[Y:%.*]], ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] {
9+
; CHECK-NEXT: entry:
10+
; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
11+
; CHECK: vector.ph:
12+
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[Y]], i64 0
13+
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x i64> [[BROADCAST_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer
14+
; CHECK-NEXT: [[BROADCAST_SPLATINSERT4:%.*]] = insertelement <8 x i64> poison, i64 [[X]], i64 0
15+
; CHECK-NEXT: [[BROADCAST_SPLAT5:%.*]] = shufflevector <8 x i64> [[BROADCAST_SPLATINSERT4]], <8 x i64> poison, <8 x i32> zeroinitializer
16+
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
17+
; CHECK: vector.body:
18+
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
19+
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <8 x i64> [ <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
20+
; CHECK-NEXT: [[STEP_ADD:%.*]] = add <8 x i64> [[VEC_IND]], <i64 8, i64 8, i64 8, i64 8, i64 8, i64 8, i64 8, i64 8>
21+
; CHECK-NEXT: [[STEP_ADD1:%.*]] = add <8 x i64> [[STEP_ADD]], <i64 8, i64 8, i64 8, i64 8, i64 8, i64 8, i64 8, i64 8>
22+
; CHECK-NEXT: [[STEP_ADD2:%.*]] = add <8 x i64> [[STEP_ADD1]], <i64 8, i64 8, i64 8, i64 8, i64 8, i64 8, i64 8, i64 8>
23+
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0
24+
; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 8
25+
; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 16
26+
; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 24
27+
; CHECK-NEXT: [[TMP4:%.*]] = icmp ule <8 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]]
28+
; CHECK-NEXT: [[TMP5:%.*]] = icmp ule <8 x i64> [[STEP_ADD]], [[BROADCAST_SPLAT]]
29+
; CHECK-NEXT: [[TMP6:%.*]] = icmp ule <8 x i64> [[STEP_ADD1]], [[BROADCAST_SPLAT]]
30+
; CHECK-NEXT: [[TMP7:%.*]] = icmp ule <8 x i64> [[STEP_ADD2]], [[BROADCAST_SPLAT]]
31+
; CHECK-NEXT: [[TMP8:%.*]] = xor <8 x i1> [[TMP4]], <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>
32+
; CHECK-NEXT: [[TMP9:%.*]] = xor <8 x i1> [[TMP5]], <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>
33+
; CHECK-NEXT: [[TMP10:%.*]] = xor <8 x i1> [[TMP6]], <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>
34+
; CHECK-NEXT: [[TMP11:%.*]] = xor <8 x i1> [[TMP7]], <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>
35+
; CHECK-NEXT: [[TMP12:%.*]] = or <8 x i64> [[BROADCAST_SPLAT5]], [[VEC_IND]]
36+
; CHECK-NEXT: [[TMP13:%.*]] = or <8 x i64> [[BROADCAST_SPLAT5]], [[STEP_ADD]]
37+
; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i64> [[BROADCAST_SPLAT5]], [[STEP_ADD1]]
38+
; CHECK-NEXT: [[TMP15:%.*]] = or <8 x i64> [[BROADCAST_SPLAT5]], [[STEP_ADD2]]
39+
; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[A]], i64 [[TMP0]]
40+
; CHECK-NEXT: [[TMP17:%.*]] = getelementptr i32, ptr [[A]], i64 [[TMP1]]
41+
; CHECK-NEXT: [[TMP18:%.*]] = getelementptr i32, ptr [[A]], i64 [[TMP2]]
42+
; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i32, ptr [[A]], i64 [[TMP3]]
43+
; CHECK-NEXT: [[TMP20:%.*]] = trunc <8 x i64> [[TMP12]] to <8 x i32>
44+
; CHECK-NEXT: [[TMP21:%.*]] = trunc <8 x i64> [[TMP13]] to <8 x i32>
45+
; CHECK-NEXT: [[TMP22:%.*]] = trunc <8 x i64> [[TMP14]] to <8 x i32>
46+
; CHECK-NEXT: [[TMP23:%.*]] = trunc <8 x i64> [[TMP15]] to <8 x i32>
47+
; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i32, ptr [[TMP16]], i32 0
48+
; CHECK-NEXT: [[TMP25:%.*]] = getelementptr i32, ptr [[TMP16]], i32 8
49+
; CHECK-NEXT: [[TMP26:%.*]] = getelementptr i32, ptr [[TMP16]], i32 16
50+
; CHECK-NEXT: [[TMP27:%.*]] = getelementptr i32, ptr [[TMP16]], i32 24
51+
; CHECK-NEXT: call void @llvm.masked.store.v8i32.p0(<8 x i32> [[TMP20]], ptr [[TMP24]], i32 4, <8 x i1> [[TMP8]])
52+
; CHECK-NEXT: call void @llvm.masked.store.v8i32.p0(<8 x i32> [[TMP21]], ptr [[TMP25]], i32 4, <8 x i1> [[TMP9]])
53+
; CHECK-NEXT: call void @llvm.masked.store.v8i32.p0(<8 x i32> [[TMP22]], ptr [[TMP26]], i32 4, <8 x i1> [[TMP10]])
54+
; CHECK-NEXT: call void @llvm.masked.store.v8i32.p0(<8 x i32> [[TMP23]], ptr [[TMP27]], i32 4, <8 x i1> [[TMP11]])
55+
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 32
56+
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <8 x i64> [[STEP_ADD2]], <i64 8, i64 8, i64 8, i64 8, i64 8, i64 8, i64 8, i64 8>
57+
; CHECK-NEXT: [[TMP28:%.*]] = icmp eq i64 [[INDEX_NEXT]], 96
58+
; CHECK-NEXT: br i1 [[TMP28]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
59+
; CHECK: middle.block:
60+
; CHECK-NEXT: br i1 false, label [[EXIT:%.*]], label [[SCALAR_PH]]
61+
; CHECK: scalar.ph:
62+
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 96, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
63+
; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
64+
; CHECK: loop.header:
65+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ]
66+
; CHECK-NEXT: [[CMP9_NOT:%.*]] = icmp ule i64 [[IV]], [[Y]]
67+
; CHECK-NEXT: br i1 [[CMP9_NOT]], label [[LOOP_LATCH]], label [[IF_THEN:%.*]]
68+
; CHECK: if.then:
69+
; CHECK-NEXT: [[OR:%.*]] = or i64 [[X]], [[IV]]
70+
; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[A]], i64 [[IV]]
71+
; CHECK-NEXT: [[T:%.*]] = trunc i64 [[OR]] to i32
72+
; CHECK-NEXT: store i32 [[T]], ptr [[GEP]], align 4
73+
; CHECK-NEXT: br label [[LOOP_LATCH]]
74+
; CHECK: loop.latch:
75+
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
76+
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 100
77+
; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]]
78+
; CHECK: exit:
79+
; CHECK-NEXT: ret i32 0
80+
;
81+
entry:
82+
br label %loop.header
83+
84+
loop.header:
85+
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]
86+
%cmp9.not = icmp ule i64 %iv, %y
87+
br i1 %cmp9.not, label %loop.latch, label %if.then
88+
89+
if.then:
90+
%or = or i64 %x, %iv
91+
%gep = getelementptr i32, ptr %A, i64 %iv
92+
%t = trunc i64 %or to i32
93+
store i32 %t, ptr %gep, align 4
94+
br label %loop.latch
95+
96+
loop.latch:
97+
%iv.next = add i64 %iv, 1
98+
%ec = icmp eq i64 %iv, 100
99+
br i1 %ec, label %exit, label %loop.header
100+
101+
exit:
102+
ret i32 0
103+
}
104+
105+
attributes #0 = { "min-legal-vector-width"="0" "target-cpu"="skylake-avx512" }
106+
;.
107+
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
108+
; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
109+
; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
110+
; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
111+
;.

0 commit comments

Comments
 (0)