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harviniriawandavemgreen
harviniriawan
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davemgreen
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[CodeGen] Update for scalable MemoryType in MMO (#70452)
Remove getSizeOrUnknown call when MachineMemOperand is created. For Scalable TypeSize, the MemoryType created becomes a scalable_vector. 2 MMOs that have scalable memory access can then use the updated BasicAA that understands scalable LocationSize. Original Patch by Harvin Iriawan Co-authored-by: David Green <[email protected]>
1 parent f886dfe commit 57146da

17 files changed

+165
-118
lines changed

‎llvm/include/llvm/Analysis/MemoryLocation.h

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -297,13 +297,6 @@ class MemoryLocation {
297297
return MemoryLocation(Ptr, LocationSize::beforeOrAfterPointer(), AATags);
298298
}
299299

300-
// Return the exact size if the exact size is known at compiletime,
301-
// otherwise return LocationSize::beforeOrAfterPointer().
302-
static LocationSize getSizeOrUnknown(const TypeSize &T) {
303-
return T.isScalable() ? LocationSize::beforeOrAfterPointer()
304-
: LocationSize::precise(T.getFixedValue());
305-
}
306-
307300
MemoryLocation() : Ptr(nullptr), Size(LocationSize::beforeOrAfterPointer()) {}
308301

309302
explicit MemoryLocation(const Value *Ptr, LocationSize Size,

‎llvm/include/llvm/CodeGen/MachineFunction.h

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1058,8 +1058,9 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
10581058
int64_t Offset, LocationSize Size) {
10591059
return getMachineMemOperand(
10601060
MMO, Offset,
1061-
!Size.hasValue() || Size.isScalable()
1062-
? LLT()
1061+
!Size.hasValue() ? LLT()
1062+
: Size.isScalable()
1063+
? LLT::scalable_vector(1, 8 * Size.getValue().getKnownMinValue())
10631064
: LLT::scalar(8 * Size.getValue().getKnownMinValue()));
10641065
}
10651066
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,

‎llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp

Lines changed: 25 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -128,14 +128,14 @@ bool GISelAddressing::aliasIsKnownForLoadStore(const MachineInstr &MI1,
128128
// vector objects on the stack.
129129
// BasePtr1 is PtrDiff away from BasePtr0. They alias if none of the
130130
// following situations arise:
131-
if (PtrDiff >= 0 && Size1.hasValue()) {
131+
if (PtrDiff >= 0 && Size1.hasValue() && !Size1.isScalable()) {
132132
// [----BasePtr0----]
133133
// [---BasePtr1--]
134134
// ========PtrDiff========>
135135
IsAlias = !((int64_t)Size1.getValue() <= PtrDiff);
136136
return true;
137137
}
138-
if (PtrDiff < 0 && Size2.hasValue()) {
138+
if (PtrDiff < 0 && Size2.hasValue() && !Size2.isScalable()) {
139139
// [----BasePtr0----]
140140
// [---BasePtr1--]
141141
// =====(-PtrDiff)====>
@@ -248,10 +248,20 @@ bool GISelAddressing::instMayAlias(const MachineInstr &MI,
248248
return false;
249249
}
250250

251+
// If NumBytes is scalable and offset is not 0, conservatively return may
252+
// alias
253+
if ((MUC0.NumBytes.isScalable() && MUC0.Offset != 0) ||
254+
(MUC1.NumBytes.isScalable() && MUC1.Offset != 0))
255+
return true;
256+
257+
const bool BothNotScalable =
258+
!MUC0.NumBytes.isScalable() && !MUC1.NumBytes.isScalable();
259+
251260
// Try to prove that there is aliasing, or that there is no aliasing. Either
252261
// way, we can return now. If nothing can be proved, proceed with more tests.
253262
bool IsAlias;
254-
if (GISelAddressing::aliasIsKnownForLoadStore(MI, Other, IsAlias, MRI))
263+
if (BothNotScalable &&
264+
GISelAddressing::aliasIsKnownForLoadStore(MI, Other, IsAlias, MRI))
255265
return IsAlias;
256266

257267
// The following all rely on MMO0 and MMO1 being valid.
@@ -267,12 +277,18 @@ bool GISelAddressing::instMayAlias(const MachineInstr &MI,
267277
Size1.hasValue()) {
268278
// Use alias analysis information.
269279
int64_t MinOffset = std::min(SrcValOffset0, SrcValOffset1);
270-
int64_t Overlap0 = Size0.getValue() + SrcValOffset0 - MinOffset;
271-
int64_t Overlap1 = Size1.getValue() + SrcValOffset1 - MinOffset;
272-
if (AA->isNoAlias(MemoryLocation(MUC0.MMO->getValue(), Overlap0,
273-
MUC0.MMO->getAAInfo()),
274-
MemoryLocation(MUC1.MMO->getValue(), Overlap1,
275-
MUC1.MMO->getAAInfo())))
280+
int64_t Overlap0 =
281+
Size0.getValue().getKnownMinValue() + SrcValOffset0 - MinOffset;
282+
int64_t Overlap1 =
283+
Size1.getValue().getKnownMinValue() + SrcValOffset1 - MinOffset;
284+
LocationSize Loc0 =
285+
Size0.isScalable() ? Size0 : LocationSize::precise(Overlap0);
286+
LocationSize Loc1 =
287+
Size1.isScalable() ? Size1 : LocationSize::precise(Overlap1);
288+
289+
if (AA->isNoAlias(
290+
MemoryLocation(MUC0.MMO->getValue(), Loc0, MUC0.MMO->getAAInfo()),
291+
MemoryLocation(MUC1.MMO->getValue(), Loc1, MUC1.MMO->getAAInfo())))
276292
return false;
277293
}
278294

‎llvm/lib/CodeGen/MachineInstr.cpp

Lines changed: 27 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1306,6 +1306,7 @@ static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, AAResults *AA,
13061306
LocationSize WidthB = MMOb->getSize();
13071307
bool KnownWidthA = WidthA.hasValue();
13081308
bool KnownWidthB = WidthB.hasValue();
1309+
bool BothMMONonScalable = !WidthA.isScalable() && !WidthB.isScalable();
13091310

13101311
const Value *ValA = MMOa->getValue();
13111312
const Value *ValB = MMOb->getValue();
@@ -1321,12 +1322,14 @@ static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, AAResults *AA,
13211322
SameVal = true;
13221323
}
13231324

1324-
if (SameVal) {
1325+
if (SameVal && BothMMONonScalable) {
13251326
if (!KnownWidthA || !KnownWidthB)
13261327
return true;
13271328
int64_t MaxOffset = std::max(OffsetA, OffsetB);
1328-
LocationSize LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
1329-
return (MinOffset + (int)LowWidth.getValue() > MaxOffset);
1329+
int64_t LowWidth = (MinOffset == OffsetA)
1330+
? WidthA.getValue().getKnownMinValue()
1331+
: WidthB.getValue().getKnownMinValue();
1332+
return (MinOffset + LowWidth > MaxOffset);
13301333
}
13311334

13321335
if (!AA)
@@ -1338,15 +1341,29 @@ static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, AAResults *AA,
13381341
assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
13391342
assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
13401343

1341-
int64_t OverlapA = KnownWidthA ? WidthA.getValue() + OffsetA - MinOffset
1342-
: MemoryLocation::UnknownSize;
1343-
int64_t OverlapB = KnownWidthB ? WidthB.getValue() + OffsetB - MinOffset
1344-
: MemoryLocation::UnknownSize;
1344+
// If Scalable Location Size has non-zero offset, Width + Offset does not work
1345+
// at the moment
1346+
if ((WidthA.isScalable() && OffsetA > 0) ||
1347+
(WidthB.isScalable() && OffsetB > 0))
1348+
return true;
1349+
1350+
int64_t OverlapA =
1351+
KnownWidthA ? WidthA.getValue().getKnownMinValue() + OffsetA - MinOffset
1352+
: MemoryLocation::UnknownSize;
1353+
int64_t OverlapB =
1354+
KnownWidthB ? WidthB.getValue().getKnownMinValue() + OffsetB - MinOffset
1355+
: MemoryLocation::UnknownSize;
1356+
1357+
LocationSize LocA = (WidthA.isScalable() || !KnownWidthA)
1358+
? WidthA
1359+
: LocationSize::precise(OverlapA);
1360+
LocationSize LocB = (WidthB.isScalable() || !KnownWidthB)
1361+
? WidthB
1362+
: LocationSize::precise(OverlapB);
13451363

13461364
return !AA->isNoAlias(
1347-
MemoryLocation(ValA, OverlapA, UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1348-
MemoryLocation(ValB, OverlapB,
1349-
UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1365+
MemoryLocation(ValA, LocA, UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1366+
MemoryLocation(ValB, LocB, UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
13501367
}
13511368

13521369
bool MachineInstr::mayAlias(AAResults *AA, const MachineInstr &Other,

‎llvm/lib/CodeGen/MachineOperand.cpp

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1107,12 +1107,13 @@ MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags F,
11071107
const MDNode *Ranges, SyncScope::ID SSID,
11081108
AtomicOrdering Ordering,
11091109
AtomicOrdering FailureOrdering)
1110-
: MachineMemOperand(ptrinfo, F,
1111-
!TS.hasValue() || TS.isScalable()
1112-
? LLT()
1113-
: LLT::scalar(8 * TS.getValue().getKnownMinValue()),
1114-
BaseAlignment, AAInfo, Ranges, SSID, Ordering,
1115-
FailureOrdering) {}
1110+
: MachineMemOperand(
1111+
ptrinfo, F,
1112+
!TS.hasValue() ? LLT()
1113+
: TS.isScalable()
1114+
? LLT::scalable_vector(1, 8 * TS.getValue().getKnownMinValue())
1115+
: LLT::scalar(8 * TS.getValue().getKnownMinValue()),
1116+
BaseAlignment, AAInfo, Ranges, SSID, Ordering, FailureOrdering) {}
11161117

11171118
void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
11181119
// The Value and Offset may differ due to CSE. But the flags and size

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 32 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -24200,7 +24200,7 @@ static SDValue narrowExtractedVectorLoad(SDNode *Extract, SelectionDAG &DAG) {
2420024200
// TODO: Use "BaseIndexOffset" to make this more effective.
2420124201
SDValue NewAddr = DAG.getMemBasePlusOffset(Ld->getBasePtr(), Offset, DL);
2420224202

24203-
LocationSize StoreSize = MemoryLocation::getSizeOrUnknown(VT.getStoreSize());
24203+
LocationSize StoreSize = LocationSize::precise(VT.getStoreSize());
2420424204
MachineFunction &MF = DAG.getMachineFunction();
2420524205
MachineMemOperand *MMO;
2420624206
if (Offset.isScalable()) {
@@ -27845,14 +27845,10 @@ bool DAGCombiner::mayAlias(SDNode *Op0, SDNode *Op1) const {
2784527845
: (LSN->getAddressingMode() == ISD::PRE_DEC)
2784627846
? -1 * C->getSExtValue()
2784727847
: 0;
27848-
LocationSize Size =
27849-
MemoryLocation::getSizeOrUnknown(LSN->getMemoryVT().getStoreSize());
27850-
return {LSN->isVolatile(),
27851-
LSN->isAtomic(),
27852-
LSN->getBasePtr(),
27853-
Offset /*base offset*/,
27854-
Size,
27855-
LSN->getMemOperand()};
27848+
TypeSize Size = LSN->getMemoryVT().getStoreSize();
27849+
return {LSN->isVolatile(), LSN->isAtomic(),
27850+
LSN->getBasePtr(), Offset /*base offset*/,
27851+
LocationSize::precise(Size), LSN->getMemOperand()};
2785627852
}
2785727853
if (const auto *LN = cast<LifetimeSDNode>(N))
2785827854
return {false /*isVolatile*/,
@@ -27894,6 +27890,13 @@ bool DAGCombiner::mayAlias(SDNode *Op0, SDNode *Op1) const {
2789427890
return false;
2789527891
}
2789627892

27893+
// If NumBytes is scalable and offset is not 0, conservatively return may
27894+
// alias
27895+
if ((MUC0.NumBytes.hasValue() && MUC0.NumBytes.isScalable() &&
27896+
MUC0.Offset != 0) ||
27897+
(MUC1.NumBytes.hasValue() && MUC1.NumBytes.isScalable() &&
27898+
MUC1.Offset != 0))
27899+
return true;
2789727900
// Try to prove that there is aliasing, or that there is no aliasing. Either
2789827901
// way, we can return now. If nothing can be proved, proceed with more tests.
2789927902
bool IsAlias;
@@ -27924,18 +27927,22 @@ bool DAGCombiner::mayAlias(SDNode *Op0, SDNode *Op1) const {
2792427927
Align OrigAlignment1 = MUC1.MMO->getBaseAlign();
2792527928
LocationSize Size0 = MUC0.NumBytes;
2792627929
LocationSize Size1 = MUC1.NumBytes;
27930+
2792727931
if (OrigAlignment0 == OrigAlignment1 && SrcValOffset0 != SrcValOffset1 &&
27928-
Size0.hasValue() && Size1.hasValue() && Size0 == Size1 &&
27929-
OrigAlignment0 > Size0.getValue() &&
27930-
SrcValOffset0 % Size0.getValue() == 0 &&
27931-
SrcValOffset1 % Size1.getValue() == 0) {
27932+
Size0.hasValue() && Size1.hasValue() && !Size0.isScalable() &&
27933+
!Size1.isScalable() && Size0 == Size1 &&
27934+
OrigAlignment0 > Size0.getValue().getKnownMinValue() &&
27935+
SrcValOffset0 % Size0.getValue().getKnownMinValue() == 0 &&
27936+
SrcValOffset1 % Size1.getValue().getKnownMinValue() == 0) {
2793227937
int64_t OffAlign0 = SrcValOffset0 % OrigAlignment0.value();
2793327938
int64_t OffAlign1 = SrcValOffset1 % OrigAlignment1.value();
2793427939

2793527940
// There is no overlap between these relatively aligned accesses of
2793627941
// similar size. Return no alias.
27937-
if ((OffAlign0 + (int64_t)Size0.getValue()) <= OffAlign1 ||
27938-
(OffAlign1 + (int64_t)Size1.getValue()) <= OffAlign0)
27942+
if ((OffAlign0 + static_cast<int64_t>(
27943+
Size0.getValue().getKnownMinValue())) <= OffAlign1 ||
27944+
(OffAlign1 + static_cast<int64_t>(
27945+
Size1.getValue().getKnownMinValue())) <= OffAlign0)
2793927946
return false;
2794027947
}
2794127948

@@ -27952,12 +27959,18 @@ bool DAGCombiner::mayAlias(SDNode *Op0, SDNode *Op1) const {
2795227959
Size0.hasValue() && Size1.hasValue()) {
2795327960
// Use alias analysis information.
2795427961
int64_t MinOffset = std::min(SrcValOffset0, SrcValOffset1);
27955-
int64_t Overlap0 = Size0.getValue() + SrcValOffset0 - MinOffset;
27956-
int64_t Overlap1 = Size1.getValue() + SrcValOffset1 - MinOffset;
27962+
int64_t Overlap0 =
27963+
Size0.getValue().getKnownMinValue() + SrcValOffset0 - MinOffset;
27964+
int64_t Overlap1 =
27965+
Size1.getValue().getKnownMinValue() + SrcValOffset1 - MinOffset;
27966+
LocationSize Loc0 =
27967+
Size0.isScalable() ? Size0 : LocationSize::precise(Overlap0);
27968+
LocationSize Loc1 =
27969+
Size1.isScalable() ? Size1 : LocationSize::precise(Overlap1);
2795727970
if (AA->isNoAlias(
27958-
MemoryLocation(MUC0.MMO->getValue(), Overlap0,
27971+
MemoryLocation(MUC0.MMO->getValue(), Loc0,
2795927972
UseTBAA ? MUC0.MMO->getAAInfo() : AAMDNodes()),
27960-
MemoryLocation(MUC1.MMO->getValue(), Overlap1,
27973+
MemoryLocation(MUC1.MMO->getValue(), Loc1,
2796127974
UseTBAA ? MUC1.MMO->getAAInfo() : AAMDNodes())))
2796227975
return false;
2796327976
}

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 9 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -8406,9 +8406,7 @@ SDValue SelectionDAG::getMemIntrinsicNode(
84068406
EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment,
84078407
MachineMemOperand::Flags Flags, LocationSize Size,
84088408
const AAMDNodes &AAInfo) {
8409-
if (Size.hasValue() && MemVT.isScalableVector())
8410-
Size = LocationSize::beforeOrAfterPointer();
8411-
else if (Size.hasValue() && !Size.getValue())
8409+
if (Size.hasValue() && !Size.getValue())
84128410
Size = LocationSize::precise(MemVT.getStoreSize());
84138411

84148412
MachineFunction &MF = getMachineFunction();
@@ -8571,7 +8569,7 @@ SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
85718569
if (PtrInfo.V.isNull())
85728570
PtrInfo = InferPointerInfo(PtrInfo, *this, Ptr, Offset);
85738571

8574-
LocationSize Size = MemoryLocation::getSizeOrUnknown(MemVT.getStoreSize());
8572+
LocationSize Size = LocationSize::precise(MemVT.getStoreSize());
85758573
MachineFunction &MF = getMachineFunction();
85768574
MachineMemOperand *MMO = MF.getMachineMemOperand(PtrInfo, MMOFlags, Size,
85778575
Alignment, AAInfo, Ranges);
@@ -8692,8 +8690,7 @@ SDValue SelectionDAG::getStore(SDValue Chain, const SDLoc &dl, SDValue Val,
86928690
PtrInfo = InferPointerInfo(PtrInfo, *this, Ptr);
86938691

86948692
MachineFunction &MF = getMachineFunction();
8695-
LocationSize Size =
8696-
MemoryLocation::getSizeOrUnknown(Val.getValueType().getStoreSize());
8693+
LocationSize Size = LocationSize::precise(Val.getValueType().getStoreSize());
86978694
MachineMemOperand *MMO =
86988695
MF.getMachineMemOperand(PtrInfo, MMOFlags, Size, Alignment, AAInfo);
86998696
return getStore(Chain, dl, Val, Ptr, MMO);
@@ -8746,8 +8743,8 @@ SDValue SelectionDAG::getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val,
87468743

87478744
MachineFunction &MF = getMachineFunction();
87488745
MachineMemOperand *MMO = MF.getMachineMemOperand(
8749-
PtrInfo, MMOFlags, MemoryLocation::getSizeOrUnknown(SVT.getStoreSize()),
8750-
Alignment, AAInfo);
8746+
PtrInfo, MMOFlags, LocationSize::precise(SVT.getStoreSize()), Alignment,
8747+
AAInfo);
87518748
return getTruncStore(Chain, dl, Val, Ptr, SVT, MMO);
87528749
}
87538750

@@ -8841,7 +8838,7 @@ SDValue SelectionDAG::getLoadVP(
88418838
if (PtrInfo.V.isNull())
88428839
PtrInfo = InferPointerInfo(PtrInfo, *this, Ptr, Offset);
88438840

8844-
LocationSize Size = MemoryLocation::getSizeOrUnknown(MemVT.getStoreSize());
8841+
LocationSize Size = LocationSize::precise(MemVT.getStoreSize());
88458842
MachineFunction &MF = getMachineFunction();
88468843
MachineMemOperand *MMO = MF.getMachineMemOperand(PtrInfo, MMOFlags, Size,
88478844
Alignment, AAInfo, Ranges);
@@ -8994,8 +8991,8 @@ SDValue SelectionDAG::getTruncStoreVP(SDValue Chain, const SDLoc &dl,
89948991

89958992
MachineFunction &MF = getMachineFunction();
89968993
MachineMemOperand *MMO = MF.getMachineMemOperand(
8997-
PtrInfo, MMOFlags, MemoryLocation::getSizeOrUnknown(SVT.getStoreSize()),
8998-
Alignment, AAInfo);
8994+
PtrInfo, MMOFlags, LocationSize::precise(SVT.getStoreSize()), Alignment,
8995+
AAInfo);
89998996
return getTruncStoreVP(Chain, dl, Val, Ptr, Mask, EVL, SVT, MMO,
90008997
IsCompressing);
90018998
}
@@ -11734,10 +11731,9 @@ MemSDNode::MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl,
1173411731
// We check here that the size of the memory operand fits within the size of
1173511732
// the MMO. This is because the MMO might indicate only a possible address
1173611733
// range instead of specifying the affected memory addresses precisely.
11737-
// TODO: Make MachineMemOperands aware of scalable vectors.
1173811734
assert(
1173911735
(!MMO->getType().isValid() ||
11740-
memvt.getStoreSize().getKnownMinValue() <= MMO->getSize().getValue()) &&
11736+
TypeSize::isKnownLE(memvt.getStoreSize(), MMO->getSize().getValue())) &&
1174111737
"Size mismatch!");
1174211738
}
1174311739

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -106,8 +106,6 @@ bool BaseIndexOffset::computeAliasing(const SDNode *Op0,
106106
int64_t PtrDiff;
107107
if (BasePtr0.equalBaseIndex(BasePtr1, DAG, PtrDiff)) {
108108
// If the size of memory access is unknown, do not use it to analysis.
109-
// One example of unknown size memory access is to load/store scalable
110-
// vector objects on the stack.
111109
// BasePtr1 is PtrDiff away from BasePtr0. They alias if none of the
112110
// following situations arise:
113111
if (PtrDiff >= 0 && NumBytes0.hasValue() && !NumBytes0.isScalable()) {

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4962,7 +4962,8 @@ void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
49624962
unsigned AS = Ptr->getType()->getScalarType()->getPointerAddressSpace();
49634963
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
49644964
MachinePointerInfo(AS), MachineMemOperand::MOLoad,
4965-
LocationSize::beforeOrAfterPointer(), Alignment, I.getAAMetadata(), Ranges);
4965+
LocationSize::beforeOrAfterPointer(), Alignment, I.getAAMetadata(),
4966+
Ranges);
49664967

49674968
if (!UniformBase) {
49684969
Base = DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2687,10 +2687,7 @@ bool AArch64InstrInfo::getMemOperandsWithOffsetWidth(
26872687
return false;
26882688
// The maximum vscale is 16 under AArch64, return the maximal extent for the
26892689
// vector.
2690-
Width = WidthN.isScalable()
2691-
? WidthN.getKnownMinValue() * AArch64::SVEMaxBitsPerVector /
2692-
AArch64::SVEBitsPerBlock
2693-
: WidthN.getKnownMinValue();
2690+
Width = LocationSize::precise(WidthN);
26942691
BaseOps.push_back(BaseOp);
26952692
return true;
26962693
}

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