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[RISCV][GISel] Support fptoi and itofp for Zfh. (#96707)
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13 files changed

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13 files changed

+1351
-9
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 12 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -423,16 +423,19 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
423423
FConstantActions.legalFor({s16});
424424
FConstantActions.lowerFor({s32, s64});
425425

426-
getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
427-
.legalIf(all(typeInSet(0, {s32, sXLen}), typeIsScalarFPArith(1, ST)))
428-
.widenScalarToNextPow2(0)
429-
.clampScalar(0, s32, sXLen)
430-
.libcall();
426+
auto &FPToIActions =
427+
getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
428+
.legalIf(all(typeInSet(0, {s32, sXLen}), typeIsScalarFPArith(1, ST)));
429+
if (ST.hasStdExtZfh())
430+
FPToIActions.legalFor({{s32, s16}, {sXLen, s16}});
431+
FPToIActions.widenScalarToNextPow2(0).clampScalar(0, s32, sXLen).libcall();
431432

432-
getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
433-
.legalIf(all(typeIsScalarFPArith(0, ST), typeInSet(1, {s32, sXLen})))
434-
.widenScalarToNextPow2(1)
435-
.clampScalar(1, s32, sXLen);
433+
auto &IToFPActions =
434+
getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
435+
.legalIf(all(typeIsScalarFPArith(0, ST), typeInSet(1, {s32, sXLen})));
436+
if (ST.hasStdExtZfh())
437+
IToFPActions.legalFor({{s16, s32}, {s16, sXLen}});
438+
IToFPActions.widenScalarToNextPow2(1).clampScalar(1, s32, sXLen);
436439

437440
// FIXME: We can do custom inline expansion like SelectionDAG.
438441
// FIXME: Legal with Zfa.

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-f16-rv32.mir

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,48 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=instruction-select \
3+
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
4+
5+
---
6+
name: fptosi_s32_s16
7+
legalized: true
8+
regBankSelected: true
9+
tracksRegLiveness: true
10+
body: |
11+
bb.1:
12+
liveins: $f10_h
13+
14+
; CHECK-LABEL: name: fptosi_s32_s16
15+
; CHECK: liveins: $f10_h
16+
; CHECK-NEXT: {{ $}}
17+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
18+
; CHECK-NEXT: [[FCVT_W_H:%[0-9]+]]:gpr = nofpexcept FCVT_W_H [[COPY]], 1
19+
; CHECK-NEXT: $x10 = COPY [[FCVT_W_H]]
20+
; CHECK-NEXT: PseudoRET implicit $x10
21+
%0:fprb(s16) = COPY $f10_h
22+
%1:gprb(s32) = G_FPTOSI %0(s16)
23+
$x10 = COPY %1(s32)
24+
PseudoRET implicit $x10
25+
26+
...
27+
---
28+
name: fptoui_s32_s16
29+
legalized: true
30+
regBankSelected: true
31+
tracksRegLiveness: true
32+
body: |
33+
bb.1:
34+
liveins: $f10_h
35+
36+
; CHECK-LABEL: name: fptoui_s32_s16
37+
; CHECK: liveins: $f10_h
38+
; CHECK-NEXT: {{ $}}
39+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
40+
; CHECK-NEXT: [[FCVT_WU_H:%[0-9]+]]:gpr = nofpexcept FCVT_WU_H [[COPY]], 1
41+
; CHECK-NEXT: $x10 = COPY [[FCVT_WU_H]]
42+
; CHECK-NEXT: PseudoRET implicit $x10
43+
%0:fprb(s16) = COPY $f10_h
44+
%1:gprb(s32) = G_FPTOUI %0(s16)
45+
$x10 = COPY %1(s32)
46+
PseudoRET implicit $x10
47+
48+
...

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-f16-rv64.mir

Lines changed: 94 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,94 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=instruction-select \
3+
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
4+
5+
---
6+
name: fptosi_s32_s16
7+
legalized: true
8+
regBankSelected: true
9+
tracksRegLiveness: true
10+
body: |
11+
bb.1:
12+
liveins: $f10_h
13+
14+
; CHECK-LABEL: name: fptosi_s32_s16
15+
; CHECK: liveins: $f10_h
16+
; CHECK-NEXT: {{ $}}
17+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
18+
; CHECK-NEXT: [[FCVT_W_H:%[0-9]+]]:gpr = nofpexcept FCVT_W_H [[COPY]], 1
19+
; CHECK-NEXT: $x10 = COPY [[FCVT_W_H]]
20+
; CHECK-NEXT: PseudoRET implicit $x10
21+
%0:fprb(s16) = COPY $f10_h
22+
%1:gprb(s32) = G_FPTOSI %0(s16)
23+
%2:gprb(s64) = G_ANYEXT %1(s32)
24+
$x10 = COPY %2(s64)
25+
PseudoRET implicit $x10
26+
27+
...
28+
---
29+
name: fptoui_s32_s16
30+
legalized: true
31+
regBankSelected: true
32+
tracksRegLiveness: true
33+
body: |
34+
bb.1:
35+
liveins: $f10_h
36+
37+
; CHECK-LABEL: name: fptoui_s32_s16
38+
; CHECK: liveins: $f10_h
39+
; CHECK-NEXT: {{ $}}
40+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
41+
; CHECK-NEXT: [[FCVT_WU_H:%[0-9]+]]:gpr = nofpexcept FCVT_WU_H [[COPY]], 1
42+
; CHECK-NEXT: $x10 = COPY [[FCVT_WU_H]]
43+
; CHECK-NEXT: PseudoRET implicit $x10
44+
%0:fprb(s16) = COPY $f10_h
45+
%1:gprb(s32) = G_FPTOUI %0(s16)
46+
%2:gprb(s64) = G_ANYEXT %1(s32)
47+
$x10 = COPY %2(s64)
48+
PseudoRET implicit $x10
49+
50+
...
51+
---
52+
name: fptosi_s64_s16
53+
legalized: true
54+
regBankSelected: true
55+
tracksRegLiveness: true
56+
body: |
57+
bb.1:
58+
liveins: $f10_h
59+
60+
; CHECK-LABEL: name: fptosi_s64_s16
61+
; CHECK: liveins: $f10_h
62+
; CHECK-NEXT: {{ $}}
63+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
64+
; CHECK-NEXT: [[FCVT_L_H:%[0-9]+]]:gpr = nofpexcept FCVT_L_H [[COPY]], 1
65+
; CHECK-NEXT: $x10 = COPY [[FCVT_L_H]]
66+
; CHECK-NEXT: PseudoRET implicit $x10
67+
%0:fprb(s16) = COPY $f10_h
68+
%1:gprb(s64) = G_FPTOSI %0(s16)
69+
$x10 = COPY %1(s64)
70+
PseudoRET implicit $x10
71+
72+
...
73+
---
74+
name: fptoui_s64_s16
75+
legalized: true
76+
regBankSelected: true
77+
tracksRegLiveness: true
78+
body: |
79+
bb.1:
80+
liveins: $f10_h
81+
82+
; CHECK-LABEL: name: fptoui_s64_s16
83+
; CHECK: liveins: $f10_h
84+
; CHECK-NEXT: {{ $}}
85+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
86+
; CHECK-NEXT: [[FCVT_LU_H:%[0-9]+]]:gpr = nofpexcept FCVT_LU_H [[COPY]], 1
87+
; CHECK-NEXT: $x10 = COPY [[FCVT_LU_H]]
88+
; CHECK-NEXT: PseudoRET implicit $x10
89+
%0:fprb(s16) = COPY $f10_h
90+
%1:gprb(s64) = G_FPTOUI %0(s16)
91+
$x10 = COPY %1(s64)
92+
PseudoRET implicit $x10
93+
94+
...

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv32.mir

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,48 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=instruction-select \
3+
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
4+
5+
---
6+
name: sitofp_s16_s32
7+
legalized: true
8+
regBankSelected: true
9+
tracksRegLiveness: true
10+
body: |
11+
bb.0:
12+
liveins: $x10
13+
14+
; CHECK-LABEL: name: sitofp_s16_s32
15+
; CHECK: liveins: $x10
16+
; CHECK-NEXT: {{ $}}
17+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
18+
; CHECK-NEXT: [[FCVT_H_W:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_W [[COPY]], 7
19+
; CHECK-NEXT: $f10_h = COPY [[FCVT_H_W]]
20+
; CHECK-NEXT: PseudoRET implicit $f10_h
21+
%0:gprb(s32) = COPY $x10
22+
%1:fprb(s16) = G_SITOFP %0(s32)
23+
$f10_h = COPY %1(s16)
24+
PseudoRET implicit $f10_h
25+
26+
...
27+
---
28+
name: uitofp_s16_s32
29+
legalized: true
30+
regBankSelected: true
31+
tracksRegLiveness: true
32+
body: |
33+
bb.0:
34+
liveins: $x10
35+
36+
; CHECK-LABEL: name: uitofp_s16_s32
37+
; CHECK: liveins: $x10
38+
; CHECK-NEXT: {{ $}}
39+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
40+
; CHECK-NEXT: [[FCVT_H_WU:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_WU [[COPY]], 7
41+
; CHECK-NEXT: $f10_h = COPY [[FCVT_H_WU]]
42+
; CHECK-NEXT: PseudoRET implicit $f10_h
43+
%0:gprb(s32) = COPY $x10
44+
%1:fprb(s16) = G_UITOFP %0(s32)
45+
$f10_h = COPY %1(s16)
46+
PseudoRET implicit $f10_h
47+
48+
...

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv64.mir

Lines changed: 94 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,94 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=instruction-select \
3+
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
4+
5+
---
6+
name: sitofp_s64_s32
7+
legalized: true
8+
regBankSelected: true
9+
tracksRegLiveness: true
10+
body: |
11+
bb.0:
12+
liveins: $x10
13+
14+
; CHECK-LABEL: name: sitofp_s64_s32
15+
; CHECK: liveins: $x10
16+
; CHECK-NEXT: {{ $}}
17+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
18+
; CHECK-NEXT: [[FCVT_H_W:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_W [[COPY]], 7
19+
; CHECK-NEXT: $f10_h = COPY [[FCVT_H_W]]
20+
; CHECK-NEXT: PseudoRET implicit $f10_h
21+
%0:gprb(s64) = COPY $x10
22+
%1:gprb(s32) = G_TRUNC %0(s64)
23+
%2:fprb(s16) = G_SITOFP %1(s32)
24+
$f10_h = COPY %2(s16)
25+
PseudoRET implicit $f10_h
26+
27+
...
28+
---
29+
name: uitofp_s64_s32
30+
legalized: true
31+
regBankSelected: true
32+
tracksRegLiveness: true
33+
body: |
34+
bb.0:
35+
liveins: $x10
36+
37+
; CHECK-LABEL: name: uitofp_s64_s32
38+
; CHECK: liveins: $x10
39+
; CHECK-NEXT: {{ $}}
40+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
41+
; CHECK-NEXT: [[FCVT_H_WU:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_WU [[COPY]], 7
42+
; CHECK-NEXT: $f10_h = COPY [[FCVT_H_WU]]
43+
; CHECK-NEXT: PseudoRET implicit $f10_h
44+
%0:gprb(s64) = COPY $x10
45+
%1:gprb(s32) = G_TRUNC %0(s64)
46+
%2:fprb(s16) = G_UITOFP %1(s32)
47+
$f10_h = COPY %2(s16)
48+
PseudoRET implicit $f10_h
49+
50+
...
51+
---
52+
name: sitofp_s64_s64
53+
legalized: true
54+
regBankSelected: true
55+
tracksRegLiveness: true
56+
body: |
57+
bb.0:
58+
liveins: $x10
59+
60+
; CHECK-LABEL: name: sitofp_s64_s64
61+
; CHECK: liveins: $x10
62+
; CHECK-NEXT: {{ $}}
63+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
64+
; CHECK-NEXT: [[FCVT_H_L:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_L [[COPY]], 7
65+
; CHECK-NEXT: $f10_h = COPY [[FCVT_H_L]]
66+
; CHECK-NEXT: PseudoRET implicit $f10_h
67+
%0:gprb(s64) = COPY $x10
68+
%1:fprb(s16) = G_SITOFP %0(s64)
69+
$f10_h = COPY %1(s16)
70+
PseudoRET implicit $f10_h
71+
72+
...
73+
---
74+
name: uitofp_s64_s64
75+
legalized: true
76+
regBankSelected: true
77+
tracksRegLiveness: true
78+
body: |
79+
bb.0:
80+
liveins: $x10
81+
82+
; CHECK-LABEL: name: uitofp_s64_s64
83+
; CHECK: liveins: $x10
84+
; CHECK-NEXT: {{ $}}
85+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
86+
; CHECK-NEXT: [[FCVT_H_LU:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_LU [[COPY]], 7
87+
; CHECK-NEXT: $f10_h = COPY [[FCVT_H_LU]]
88+
; CHECK-NEXT: PseudoRET implicit $f10_h
89+
%0:gprb(s64) = COPY $x10
90+
%1:fprb(s16) = G_UITOFP %0(s64)
91+
$f10_h = COPY %1(s16)
92+
PseudoRET implicit $f10_h
93+
94+
...

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