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lines changed Original file line number Diff line number Diff line change @@ -3081,7 +3081,8 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
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}
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if (RPI.isPaired () && RPI.isScalable ()) {
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- const AArch64Subtarget &Subtarget = MF.getSubtarget <AArch64Subtarget>();
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+ [[maybe_unused]] const AArch64Subtarget &Subtarget =
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+ MF.getSubtarget <AArch64Subtarget>();
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AArch64FunctionInfo *AFI = MF.getInfo <AArch64FunctionInfo>();
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unsigned PnReg = AFI->getPredicateRegForFillSpill ();
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assert (((Subtarget.hasSVE2p1 () || Subtarget.hasSME2 ()) && PnReg != 0 ) &&
@@ -3250,7 +3251,8 @@ bool AArch64FrameLowering::restoreCalleeSavedRegisters(
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AArch64FunctionInfo *AFI = MF.getInfo <AArch64FunctionInfo>();
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if (RPI.isPaired () && RPI.isScalable ()) {
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- const AArch64Subtarget &Subtarget = MF.getSubtarget <AArch64Subtarget>();
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+ [[maybe_unused]] const AArch64Subtarget &Subtarget =
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+ MF.getSubtarget <AArch64Subtarget>();
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unsigned PnReg = AFI->getPredicateRegForFillSpill ();
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assert (((Subtarget.hasSVE2p1 () || Subtarget.hasSME2 ()) && PnReg != 0 ) &&
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" Expects SVE2.1 or SME2 target and a predicate register" );
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