Skip to content

Commit 5a2ccfc

Browse files
SpencerAbsonSpencerAbson
committed
[AArch64] Implement intrinsics for SME FP8 FMLAL/FMLALL
1 parent 411f907 commit 5a2ccfc

File tree

8 files changed

+503
-148
lines changed

8 files changed

+503
-148
lines changed

‎clang/include/clang/Basic/arm_sme.td

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -827,11 +827,27 @@ let SMETargetGuard = "sme-lutv2" in {
827827
let SMETargetGuard = "sme-f8f32" in {
828828
def SVMOPA_FP8_ZA32 : Inst<"svmopa_za32[_mf8]_m_fpm", "viPPdd>", "m", MergeNone, "aarch64_sme_fp8_fmopa_za32",
829829
[IsStreaming, IsInOutZA, SetsFPMR, IsOverloadNone], [ImmCheck<0, ImmCheck0_3>]>;
830+
831+
// FMLALL (indexed)
832+
def SVMLA_FP8_ZA32_VG4x1 : Inst<"svmla_lane_za32[_mf8]_vg4x1_fpm", "vmddi>", "m", MergeNone, "aarch64_sme_fp8_fmlall_lane_za32_vg4x1",
833+
[IsStreaming, IsInOutZA, SetsFPMR, IsOverloadNone], [ImmCheck<3, ImmCheck0_15>]>;
834+
def SVMLA_FP8_ZA32_VG4x2 : Inst<"svmla_lane_za32[_mf8]_vg4x2_fpm", "vm2di>", "m", MergeNone, "aarch64_sme_fp8_fmlall_lane_za32_vg4x2",
835+
[IsStreaming, IsInOutZA, SetsFPMR, IsOverloadNone], [ImmCheck<3, ImmCheck0_15>]>;
836+
def SVMLA_FP8_ZA16_VG4x4 : Inst<"svmla_lane_za32[_mf8]_vg4x4_fpm", "vm4di>", "m", MergeNone, "aarch64_sme_fp8_fmlall_lane_za32_vg4x4",
837+
[IsStreaming, IsInOutZA, SetsFPMR, IsOverloadNone], [ImmCheck<3, ImmCheck0_15>]>;
830838
}
831839

832840
let SMETargetGuard = "sme-f8f16" in {
833841
def SVMOPA_FP8_ZA16 : Inst<"svmopa_za16[_mf8]_m_fpm", "viPPdd>", "m", MergeNone, "aarch64_sme_fp8_fmopa_za16",
834842
[IsStreaming, IsInOutZA, SetsFPMR, IsOverloadNone], [ImmCheck<0, ImmCheck0_1>]>;
843+
844+
// FMLAL (indexed)
845+
def SVMLA_FP8_ZA16_VG2x1 : Inst<"svmla_lane_za16[_mf8]_vg2x1_fpm", "vmddi>", "m", MergeNone, "aarch64_sme_fp8_fmlal_lane_za16_vg2x1",
846+
[IsStreaming, IsInOutZA, SetsFPMR, IsOverloadNone], [ImmCheck<3, ImmCheck0_15>]>;
847+
def SVMLA_FP8_ZA16_VG2x2 : Inst<"svmla_lane_za16[_mf8]_vg2x2_fpm", "vm2di>", "m", MergeNone, "aarch64_sme_fp8_fmlal_lane_za16_vg2x2",
848+
[IsStreaming, IsInOutZA, SetsFPMR, IsOverloadNone], [ImmCheck<3, ImmCheck0_15>]>;
849+
def SVMLA_FP8_ZA16_VG2x4 : Inst<"svmla_lane_za16[_mf8]_vg2x4_fpm", "vm4di>", "m", MergeNone, "aarch64_sme_fp8_fmlal_lane_za16_vg2x4",
850+
[IsStreaming, IsInOutZA, SetsFPMR, IsOverloadNone], [ImmCheck<3, ImmCheck0_15>]>;
835851
}
836852

837853
} // let SVETargetGuard = InvalidMode

‎clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c

Lines changed: 128 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,128 @@
1+
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
2+
// REQUIRES: aarch64-registered-target
3+
4+
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s
5+
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
6+
// RUN: %clang_cc1 -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s
7+
// RUN: %clang_cc1 -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
8+
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
9+
10+
#include <arm_sme.h>
11+
12+
#ifdef SME_OVERLOADED_FORMS
13+
#define SME_ACLE_FUNC(A1,A2_UNUSED,A3) A1##A3
14+
#else
15+
#define SME_ACLE_FUNC(A1,A2,A3) A1##A2##A3
16+
#endif
17+
18+
// FMLAL (indexed)
19+
20+
// CHECK-LABEL: define dso_local void @test_svmla_lane_za16_vg2x1(
21+
// CHECK-SAME: i32 noundef [[SLICE:%.*]], <vscale x 16 x i8> [[ZN:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0:[0-9]+]] {
22+
// CHECK-NEXT: [[ENTRY:.*:]]
23+
// CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]])
24+
// CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x1(i32 [[SLICE]], <vscale x 16 x i8> [[ZN]], <vscale x 16 x i8> [[ZM]], i32 0)
25+
// CHECK-NEXT: ret void
26+
//
27+
// CPP-CHECK-LABEL: define dso_local void @_Z26test_svmla_lane_za16_vg2x1ju13__SVMfloat8_tS_m(
28+
// CPP-CHECK-SAME: i32 noundef [[SLICE:%.*]], <vscale x 16 x i8> [[ZN:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0:[0-9]+]] {
29+
// CPP-CHECK-NEXT: [[ENTRY:.*:]]
30+
// CPP-CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]])
31+
// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x1(i32 [[SLICE]], <vscale x 16 x i8> [[ZN]], <vscale x 16 x i8> [[ZM]], i32 0)
32+
// CPP-CHECK-NEXT: ret void
33+
//
34+
void test_svmla_lane_za16_vg2x1(uint32_t slice, svmfloat8_t zn, svmfloat8_t zm, fpm_t fpm) __arm_streaming __arm_inout("za") {
35+
SME_ACLE_FUNC(svmla_lane_za16,_mf8,_vg2x1_fpm)(slice, zn, zm, 0, fpm);
36+
}
37+
38+
// CHECK-LABEL: define dso_local void @test_svmla_lane_za16_vg2x2(
39+
// CHECK-SAME: i32 noundef [[SLICE:%.*]], <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
40+
// CHECK-NEXT: [[ENTRY:.*:]]
41+
// CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]])
42+
// CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x2(i32 [[SLICE]], <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZM]], i32 15)
43+
// CHECK-NEXT: ret void
44+
//
45+
// CPP-CHECK-LABEL: define dso_local void @_Z26test_svmla_lane_za16_vg2x2j13svmfloat8x2_tu13__SVMfloat8_tm(
46+
// CPP-CHECK-SAME: i32 noundef [[SLICE:%.*]], <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
47+
// CPP-CHECK-NEXT: [[ENTRY:.*:]]
48+
// CPP-CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]])
49+
// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x2(i32 [[SLICE]], <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZM]], i32 15)
50+
// CPP-CHECK-NEXT: ret void
51+
//
52+
void test_svmla_lane_za16_vg2x2(uint32_t slice, svmfloat8x2_t zn, svmfloat8_t zm, fpm_t fpm) __arm_streaming __arm_inout("za") {
53+
SME_ACLE_FUNC(svmla_lane_za16,_mf8,_vg2x2_fpm)(slice, zn, zm, 15, fpm);
54+
}
55+
56+
// CHECK-LABEL: define dso_local void @test_svmla_lane_za16_vg2x4(
57+
// CHECK-SAME: i32 noundef [[SLICE:%.*]], <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZN_COERCE2:%.*]], <vscale x 16 x i8> [[ZN_COERCE3:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
58+
// CHECK-NEXT: [[ENTRY:.*:]]
59+
// CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]])
60+
// CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x4(i32 [[SLICE]], <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZN_COERCE2]], <vscale x 16 x i8> [[ZN_COERCE3]], <vscale x 16 x i8> [[ZM]], i32 7)
61+
// CHECK-NEXT: ret void
62+
//
63+
// CPP-CHECK-LABEL: define dso_local void @_Z26test_svmla_lane_za16_vg2x4j13svmfloat8x4_tu13__SVMfloat8_tm(
64+
// CPP-CHECK-SAME: i32 noundef [[SLICE:%.*]], <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZN_COERCE2:%.*]], <vscale x 16 x i8> [[ZN_COERCE3:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
65+
// CPP-CHECK-NEXT: [[ENTRY:.*:]]
66+
// CPP-CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]])
67+
// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x4(i32 [[SLICE]], <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZN_COERCE2]], <vscale x 16 x i8> [[ZN_COERCE3]], <vscale x 16 x i8> [[ZM]], i32 7)
68+
// CPP-CHECK-NEXT: ret void
69+
//
70+
void test_svmla_lane_za16_vg2x4(uint32_t slice, svmfloat8x4_t zn, svmfloat8_t zm, fpm_t fpm) __arm_streaming __arm_inout("za") {
71+
SME_ACLE_FUNC(svmla_lane_za16,_mf8,_vg2x4_fpm)(slice, zn, zm, 7, fpm);
72+
}
73+
74+
// FMLALL (indexed)
75+
76+
// CHECK-LABEL: define dso_local void @test_svmla_lane_za32_vg4x1(
77+
// CHECK-SAME: i32 noundef [[SLICE:%.*]], <vscale x 16 x i8> [[ZN:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
78+
// CHECK-NEXT: [[ENTRY:.*:]]
79+
// CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]])
80+
// CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x1(i32 [[SLICE]], <vscale x 16 x i8> [[ZN]], <vscale x 16 x i8> [[ZM]], i32 0)
81+
// CHECK-NEXT: ret void
82+
//
83+
// CPP-CHECK-LABEL: define dso_local void @_Z26test_svmla_lane_za32_vg4x1ju13__SVMfloat8_tS_m(
84+
// CPP-CHECK-SAME: i32 noundef [[SLICE:%.*]], <vscale x 16 x i8> [[ZN:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
85+
// CPP-CHECK-NEXT: [[ENTRY:.*:]]
86+
// CPP-CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]])
87+
// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x1(i32 [[SLICE]], <vscale x 16 x i8> [[ZN]], <vscale x 16 x i8> [[ZM]], i32 0)
88+
// CPP-CHECK-NEXT: ret void
89+
//
90+
void test_svmla_lane_za32_vg4x1(uint32_t slice, svmfloat8_t zn, svmfloat8_t zm, fpm_t fpm) __arm_streaming __arm_inout("za") {
91+
SME_ACLE_FUNC(svmla_lane_za32,_mf8,_vg4x1_fpm)(slice, zn, zm, 0, fpm);
92+
}
93+
94+
// CHECK-LABEL: define dso_local void @test_svmla_lane_za32_vg4x2(
95+
// CHECK-SAME: i32 noundef [[SLICE:%.*]], <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
96+
// CHECK-NEXT: [[ENTRY:.*:]]
97+
// CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]])
98+
// CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x2(i32 [[SLICE]], <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZM]], i32 15)
99+
// CHECK-NEXT: ret void
100+
//
101+
// CPP-CHECK-LABEL: define dso_local void @_Z26test_svmla_lane_za32_vg4x2j13svmfloat8x2_tu13__SVMfloat8_tm(
102+
// CPP-CHECK-SAME: i32 noundef [[SLICE:%.*]], <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
103+
// CPP-CHECK-NEXT: [[ENTRY:.*:]]
104+
// CPP-CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]])
105+
// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x2(i32 [[SLICE]], <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZM]], i32 15)
106+
// CPP-CHECK-NEXT: ret void
107+
//
108+
void test_svmla_lane_za32_vg4x2(uint32_t slice, svmfloat8x2_t zn, svmfloat8_t zm, fpm_t fpm) __arm_streaming __arm_inout("za") {
109+
SME_ACLE_FUNC(svmla_lane_za32,_mf8,_vg4x2_fpm)(slice, zn, zm, 15, fpm);
110+
}
111+
112+
// CHECK-LABEL: define dso_local void @test_svmla_lane_za32_vg4x4(
113+
// CHECK-SAME: i32 noundef [[SLICE:%.*]], <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZN_COERCE2:%.*]], <vscale x 16 x i8> [[ZN_COERCE3:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
114+
// CHECK-NEXT: [[ENTRY:.*:]]
115+
// CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]])
116+
// CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x4(i32 [[SLICE]], <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZN_COERCE2]], <vscale x 16 x i8> [[ZN_COERCE3]], <vscale x 16 x i8> [[ZM]], i32 7)
117+
// CHECK-NEXT: ret void
118+
//
119+
// CPP-CHECK-LABEL: define dso_local void @_Z26test_svmla_lane_za32_vg4x4j13svmfloat8x4_tu13__SVMfloat8_tm(
120+
// CPP-CHECK-SAME: i32 noundef [[SLICE:%.*]], <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZN_COERCE2:%.*]], <vscale x 16 x i8> [[ZN_COERCE3:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
121+
// CPP-CHECK-NEXT: [[ENTRY:.*:]]
122+
// CPP-CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]])
123+
// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x4(i32 [[SLICE]], <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZN_COERCE2]], <vscale x 16 x i8> [[ZN_COERCE3]], <vscale x 16 x i8> [[ZM]], i32 7)
124+
// CPP-CHECK-NEXT: ret void
125+
//
126+
void test_svmla_lane_za32_vg4x4(uint32_t slice, svmfloat8x4_t zn, svmfloat8_t zm, fpm_t fpm) __arm_streaming __arm_inout("za") {
127+
SME_ACLE_FUNC(svmla_lane_za32,_mf8,_vg4x4_fpm)(slice, zn, zm, 7, fpm);
128+
}

‎clang/test/Sema/aarch64-fp8-intrinsics/acle_sme2_fp8_imm.c

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,3 +16,37 @@ void test_svmopa(svbool_t pn, svbool_t pm, svmfloat8_t zn, svmfloat8_t zm,
1616
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
1717
svmopa_za32_mf8_m_fpm(4, pn, pm, zn, zm, fpmr);
1818
}
19+
20+
void test_svmla(uint32_t slice, svmfloat8_t zn, svmfloat8x2_t znx2, svmfloat8x4_t znx4,
21+
fpm_t fpmr) __arm_streaming __arm_inout("za") {
22+
// expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 15]}}
23+
svmla_lane_za16_mf8_vg2x1_fpm(slice, zn, zn, -1, fpmr);
24+
// expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
25+
svmla_lane_za16_mf8_vg2x1_fpm(slice, zn, zn, 16, fpmr);
26+
27+
// expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 15]}}
28+
svmla_lane_za16_mf8_vg2x2_fpm(slice, znx2, zn, -1, fpmr);
29+
// expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
30+
svmla_lane_za16_mf8_vg2x2_fpm(slice, znx2, zn, 16, fpmr);
31+
32+
// expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 15]}}
33+
svmla_lane_za16_mf8_vg2x4_fpm(slice, znx4, zn, -1, fpmr);
34+
// expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
35+
svmla_lane_za16_mf8_vg2x4_fpm(slice, znx4, zn, 16, fpmr);
36+
37+
// expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 15]}}
38+
svmla_lane_za32_mf8_vg4x1_fpm(slice, zn, zn, -1, fpmr);
39+
// expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
40+
svmla_lane_za32_mf8_vg4x1_fpm(slice, zn, zn, 16, fpmr);
41+
42+
// expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 15]}}
43+
svmla_lane_za32_mf8_vg4x2_fpm(slice, znx2, zn, -1, fpmr);
44+
// expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
45+
svmla_lane_za32_mf8_vg4x2_fpm(slice, znx2, zn, 16, fpmr);
46+
47+
// expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 15]}}
48+
svmla_lane_za32_mf8_vg4x4_fpm(slice, znx4, zn, -1, fpmr);
49+
// expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
50+
svmla_lane_za32_mf8_vg4x4_fpm(slice, znx4, zn, 16, fpmr);
51+
52+
}

‎clang/test/Sema/aarch64-fp8-intrinsics/acle_sme_fp8_mla.c

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -verify -emit-llvm-only %s
2+
3+
// REQUIRES: aarch64-registered-target
4+
5+
#include <arm_sme.h>
6+
7+
void test_svmla(uint32_t slice, svmfloat8_t zn, svmfloat8x2_t znx2, svmfloat8x4_t znx4,
8+
fpm_t fpmr) __arm_streaming __arm_inout("za") {
9+
// expected-error@+1 {{'svmla_lane_za16_mf8_vg2x1_fpm' needs target feature sme,sme-f8f16}}
10+
svmla_lane_za16_mf8_vg2x1_fpm(slice, zn, zn, 0, fpmr);
11+
12+
// expected-error@+1 {{'svmla_lane_za16_mf8_vg2x2_fpm' needs target feature sme,sme-f8f16}}
13+
svmla_lane_za16_mf8_vg2x2_fpm(slice, znx2, zn, 0, fpmr);
14+
15+
// expected-error@+1 {{'svmla_lane_za16_mf8_vg2x4_fpm' needs target feature sme,sme-f8f16}}
16+
svmla_lane_za16_mf8_vg2x4_fpm(slice, znx4, zn, 0, fpmr);
17+
18+
// expected-error@+1 {{'svmla_lane_za32_mf8_vg4x1_fpm' needs target feature sme,sme-f8f32}}
19+
svmla_lane_za32_mf8_vg4x1_fpm(slice, zn, zn, 0, fpmr);
20+
21+
// expected-error@+1 {{'svmla_lane_za32_mf8_vg4x2_fpm' needs target feature sme,sme-f8f32}}
22+
svmla_lane_za32_mf8_vg4x2_fpm(slice, znx2, zn, 0, fpmr);
23+
24+
// expected-error@+1 {{'svmla_lane_za32_mf8_vg4x4_fpm' needs target feature sme,sme-f8f32}}
25+
svmla_lane_za32_mf8_vg4x4_fpm(slice, znx4, zn, 0, fpmr);
26+
}

‎llvm/include/llvm/IR/IntrinsicsAArch64.td

Lines changed: 55 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -3870,31 +3870,66 @@ def int_aarch64_neon_famin : AdvSIMD_2VectorArg_Intrinsic;
38703870
// FP8 Intrinsics
38713871
//
38723872
let TargetPrefix = "aarch64" in {
3873-
3874-
class SME2_FP8_CVT_X2_Single_Intrinsic
3875-
: DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
3876-
[llvm_nxv16i8_ty],
3877-
[IntrReadMem, IntrInaccessibleMemOnly]>;
3878-
3873+
38793874
class SME_FP8_OuterProduct_Intrinsic
38803875
: DefaultAttrsIntrinsic<[],
38813876
[llvm_i32_ty,
38823877
llvm_nxv16i1_ty, llvm_nxv16i1_ty,
38833878
llvm_nxv16i8_ty, llvm_nxv16i8_ty],
38843879
[ImmArg<ArgIndex<0>>, IntrInaccessibleMemOnly, IntrHasSideEffects]>;
3885-
//
3886-
// CVT from FP8 to half-precision/BFloat16 multi-vector
3887-
//
3888-
def int_aarch64_sve_fp8_cvt1_x2 : SME2_FP8_CVT_X2_Single_Intrinsic;
3889-
def int_aarch64_sve_fp8_cvt2_x2 : SME2_FP8_CVT_X2_Single_Intrinsic;
38903880

3891-
//
3892-
// CVT from FP8 to deinterleaved half-precision/BFloat16 multi-vector
3893-
//
3894-
def int_aarch64_sve_fp8_cvtl1_x2 : SME2_FP8_CVT_X2_Single_Intrinsic;
3895-
def int_aarch64_sve_fp8_cvtl2_x2 : SME2_FP8_CVT_X2_Single_Intrinsic;
3896-
3897-
// FP8 outer product
3898-
def int_aarch64_sme_fp8_fmopa_za16 : SME_FP8_OuterProduct_Intrinsic;
3899-
def int_aarch64_sme_fp8_fmopa_za32 : SME_FP8_OuterProduct_Intrinsic;
3881+
class SME2_FP8_CVT_X2_Single_Intrinsic
3882+
: DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
3883+
[llvm_nxv16i8_ty],
3884+
[IntrReadMem, IntrInaccessibleMemOnly]>;
3885+
3886+
class SME_FP8_ZA_LANE_VGx1 :
3887+
DefaultAttrsIntrinsic<[], [llvm_i32_ty,
3888+
llvm_nxv16i8_ty,
3889+
llvm_nxv16i8_ty,
3890+
llvm_i32_ty],
3891+
[IntrInaccessibleMemOnly, IntrHasSideEffects, ImmArg<ArgIndex<3>>]>;
3892+
3893+
class SME_FP8_ZA_LANE_VGx2 :
3894+
DefaultAttrsIntrinsic<[], [llvm_i32_ty,
3895+
llvm_nxv16i8_ty, llvm_nxv16i8_ty,
3896+
llvm_nxv16i8_ty,
3897+
llvm_i32_ty],
3898+
[IntrInaccessibleMemOnly, IntrHasSideEffects, ImmArg<ArgIndex<4>>]>;
3899+
3900+
class SME_FP8_ZA_LANE_VGx4 :
3901+
DefaultAttrsIntrinsic<[], [llvm_i32_ty,
3902+
llvm_nxv16i8_ty, llvm_nxv16i8_ty, llvm_nxv16i8_ty, llvm_nxv16i8_ty,
3903+
llvm_nxv16i8_ty,
3904+
llvm_i32_ty],
3905+
[IntrInaccessibleMemOnly, IntrHasSideEffects, ImmArg<ArgIndex<6>>]>;
3906+
3907+
//
3908+
// CVT from FP8 to half-precision/BFloat16 multi-vector
3909+
//
3910+
def int_aarch64_sve_fp8_cvt1_x2 : SME2_FP8_CVT_X2_Single_Intrinsic;
3911+
def int_aarch64_sve_fp8_cvt2_x2 : SME2_FP8_CVT_X2_Single_Intrinsic;
3912+
3913+
//
3914+
// CVT from FP8 to deinterleaved half-precision/BFloat16 multi-vector
3915+
//
3916+
def int_aarch64_sve_fp8_cvtl1_x2 : SME2_FP8_CVT_X2_Single_Intrinsic;
3917+
def int_aarch64_sve_fp8_cvtl2_x2 : SME2_FP8_CVT_X2_Single_Intrinsic;
3918+
3919+
// FP8 outer product
3920+
def int_aarch64_sme_fp8_fmopa_za16 : SME_FP8_OuterProduct_Intrinsic;
3921+
def int_aarch64_sme_fp8_fmopa_za32 : SME_FP8_OuterProduct_Intrinsic;
3922+
3923+
//
3924+
// ZA multiply-add
3925+
//
3926+
// Double-vector groups (F8F16)
3927+
def int_aarch64_sme_fp8_fmlal_lane_za16_vg2x1 : SME_FP8_ZA_LANE_VGx1;
3928+
def int_aarch64_sme_fp8_fmlal_lane_za16_vg2x2 : SME_FP8_ZA_LANE_VGx2;
3929+
def int_aarch64_sme_fp8_fmlal_lane_za16_vg2x4 : SME_FP8_ZA_LANE_VGx4;
3930+
3931+
// Quad-vector groups (F8F32)
3932+
def int_aarch64_sme_fp8_fmlall_lane_za32_vg4x1 : SME_FP8_ZA_LANE_VGx1;
3933+
def int_aarch64_sme_fp8_fmlall_lane_za32_vg4x2 : SME_FP8_ZA_LANE_VGx2;
3934+
def int_aarch64_sme_fp8_fmlall_lane_za32_vg4x4 : SME_FP8_ZA_LANE_VGx4;
39003935
}

0 commit comments

Comments
 (0)