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[VPlan] Mark VPVectorPointer as only using the first part of the ptr.
VPVectorPointerRecipe only uses the first part of the pointer operand, so mark it accordingly. Follow-up suggested as part of #99808.
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8 files changed

+9
-23
lines changed

8 files changed

+9
-23
lines changed

‎llvm/lib/Transforms/Vectorize/VPlan.h

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1673,6 +1673,14 @@ class VPVectorPointerRecipe : public VPRecipeWithIRFlags {
16731673
return true;
16741674
}
16751675

1676+
/// Returns true if the recipe only uses the first part of operand \p Op.
1677+
bool onlyFirstPartUsed(const VPValue *Op) const override {
1678+
assert(is_contained(operands(), Op) &&
1679+
"Op must be an operand of the recipe");
1680+
assert(getNumOperands() == 1 && "must have a single operand");
1681+
return true;
1682+
}
1683+
16761684
VPVectorPointerRecipe *clone() override {
16771685
return new VPVectorPointerRecipe(getOperand(0), IndexedTy, IsReverse,
16781686
isInBounds(), getDebugLoc());

‎llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -113,7 +113,6 @@ define i64 @pointer_induction_only(ptr %start, ptr %end) {
113113
; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 0
114114
; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 8
115115
; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP4]]
116-
; CHECK-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP5]]
117116
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i32 0
118117
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i32 2
119118
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP6]], align 1
@@ -176,7 +175,6 @@ define i64 @int_and_pointer_iv(ptr %start, i32 %N) {
176175
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0
177176
; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 16
178177
; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP0]]
179-
; CHECK-NEXT: [[NEXT_GEP2:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP1]]
180178
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i32 0
181179
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i32 4
182180
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4

‎llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -384,7 +384,6 @@ define void @test_pr57912_pointer_induction(ptr %start) #0 {
384384
; CHECK-NEXT: [[TMP12:%.*]] = mul i64 [[TMP11]], 1
385385
; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[INDEX]], [[TMP12]]
386386
; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[START:%.*]], i64 [[TMP8]]
387-
; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP13]]
388387
; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[TMP14]], i32 0
389388
; CHECK-NEXT: [[TMP17:%.*]] = call i64 @llvm.vscale.i64()
390389
; CHECK-NEXT: [[TMP18:%.*]] = mul i64 [[TMP17]], 16
@@ -466,7 +465,6 @@ define void @test_pr57912_pointer_induction(ptr %start) #0 {
466465
; CHECK-VF8-NEXT: [[TMP10:%.*]] = mul i64 [[TMP9]], 1
467466
; CHECK-VF8-NEXT: [[TMP11:%.*]] = add i64 [[INDEX]], [[TMP10]]
468467
; CHECK-VF8-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[START:%.*]], i64 [[TMP6]]
469-
; CHECK-VF8-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP11]]
470468
; CHECK-VF8-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[TMP12]], i32 0
471469
; CHECK-VF8-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
472470
; CHECK-VF8-NEXT: [[TMP16:%.*]] = mul i64 [[TMP15]], 16

‎llvm/test/Transforms/LoopVectorize/AArch64/sve-live-out-pointer-induction.ll

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,6 @@ define ptr @test(ptr %start.1, ptr %start.2, ptr %end) {
3636
; CHECK-NEXT: [[TMP28:%.*]] = mul i64 [[TMP27]], 8
3737
; CHECK-NEXT: [[TMP29:%.*]] = add i64 [[OFFSET_IDX]], [[TMP28]]
3838
; CHECK-NEXT: [[TMP30:%.*]] = getelementptr i8, ptr [[START_2]], i64 [[TMP24]]
39-
; CHECK-NEXT: [[TMP31:%.*]] = getelementptr i8, ptr [[START_2]], i64 [[TMP29]]
4039
; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i64, ptr [[TMP30]], i32 0
4140
; CHECK-NEXT: [[TMP33:%.*]] = call i64 @llvm.vscale.i64()
4241
; CHECK-NEXT: [[TMP34:%.*]] = mul i64 [[TMP33]], 2

‎llvm/test/Transforms/LoopVectorize/PowerPC/exit-branch-cost.ll

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -49,13 +49,6 @@ define i1 @select_exit_cond(ptr %start, ptr %end, i64 %N) {
4949
; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], 12
5050
; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[INDEX]], 14
5151
; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP3]]
52-
; CHECK-NEXT: [[NEXT_GEP18:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP4]]
53-
; CHECK-NEXT: [[NEXT_GEP19:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP5]]
54-
; CHECK-NEXT: [[NEXT_GEP20:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP6]]
55-
; CHECK-NEXT: [[NEXT_GEP21:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP7]]
56-
; CHECK-NEXT: [[NEXT_GEP22:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP8]]
57-
; CHECK-NEXT: [[NEXT_GEP23:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP9]]
58-
; CHECK-NEXT: [[NEXT_GEP24:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP10]]
5952
; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i32 0
6053
; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i32 2
6154
; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i32 4

‎llvm/test/Transforms/LoopVectorize/X86/masked-store-cost.ll

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -179,7 +179,6 @@ define void @test_scalar_cost_single_store_loop_varying_cond(ptr %dst, ptr noali
179179
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0
180180
; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 16
181181
; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP0]]
182-
; CHECK-NEXT: [[NEXT_GEP2:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP1]]
183182
; CHECK-NEXT: [[OFFSET_IDX3:%.*]] = mul i64 [[INDEX]], 4
184183
; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX3]], 0
185184
; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX3]], 16

‎llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -81,7 +81,6 @@ define void @switch_default_to_latch_common_dest(ptr %start, ptr %end) {
8181
; FORCED-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 0
8282
; FORCED-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 32
8383
; FORCED-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP5]]
84-
; FORCED-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP6]]
8584
; FORCED-NEXT: [[TMP7:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i32 0
8685
; FORCED-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i32 4
8786
; FORCED-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP7]], align 1
@@ -227,7 +226,6 @@ define void @switch_default_to_latch_common_dest_using_branches(ptr %start, ptr
227226
; FORCED-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 0
228227
; FORCED-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 32
229228
; FORCED-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP5]]
230-
; FORCED-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP6]]
231229
; FORCED-NEXT: [[TMP7:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i32 0
232230
; FORCED-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i32 4
233231
; FORCED-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP7]], align 1
@@ -354,7 +352,6 @@ define void @switch_all_dests_distinct(ptr %start, ptr %end) {
354352
; FORCED-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 0
355353
; FORCED-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 32
356354
; FORCED-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP5]]
357-
; FORCED-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP6]]
358355
; FORCED-NEXT: [[TMP7:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i32 0
359356
; FORCED-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i32 4
360357
; FORCED-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP7]], align 1
@@ -550,7 +547,6 @@ define void @switch_all_dests_distinct_variant_using_branches(ptr %start, ptr %e
550547
; FORCED-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 0
551548
; FORCED-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 32
552549
; FORCED-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP5]]
553-
; FORCED-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP6]]
554550
; FORCED-NEXT: [[TMP7:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i32 0
555551
; FORCED-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i32 4
556552
; FORCED-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP7]], align 1
@@ -714,7 +710,6 @@ define void @switch_multiple_common_dests(ptr %start, ptr %end) {
714710
; FORCED-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 0
715711
; FORCED-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 32
716712
; FORCED-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP5]]
717-
; FORCED-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP6]]
718713
; FORCED-NEXT: [[TMP7:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i32 0
719714
; FORCED-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i32 4
720715
; FORCED-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP7]], align 1
@@ -873,7 +868,6 @@ define void @switch4_default_common_dest_with_case(ptr %start, ptr %end) {
873868
; FORCED-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 0
874869
; FORCED-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 32
875870
; FORCED-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP5]]
876-
; FORCED-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP6]]
877871
; FORCED-NEXT: [[TMP7:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i32 0
878872
; FORCED-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i32 4
879873
; FORCED-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP7]], align 1
@@ -1060,7 +1054,6 @@ define void @switch_under_br_default_common_dest_with_case(ptr %start, ptr %end,
10601054
; FORCED-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 0
10611055
; FORCED-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 32
10621056
; FORCED-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP5]]
1063-
; FORCED-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP6]]
10641057
; FORCED-NEXT: [[TMP7:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i32 0
10651058
; FORCED-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i32 4
10661059
; FORCED-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP7]], align 1
@@ -1219,7 +1212,6 @@ define void @br_under_switch_default_common_dest_with_case(ptr %start, ptr %end,
12191212
; FORCED-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 0
12201213
; FORCED-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 32
12211214
; FORCED-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP5]]
1222-
; FORCED-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP6]]
12231215
; FORCED-NEXT: [[TMP7:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i32 0
12241216
; FORCED-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i32 4
12251217
; FORCED-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP7]], align 1
@@ -1377,7 +1369,6 @@ define void @large_number_of_cases(ptr %start, ptr %end) {
13771369
; FORCED-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 0
13781370
; FORCED-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 32
13791371
; FORCED-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP5]]
1380-
; FORCED-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP6]]
13811372
; FORCED-NEXT: [[TMP7:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i32 0
13821373
; FORCED-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i32 4
13831374
; FORCED-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP7]], align 1

‎llvm/test/Transforms/PhaseOrdering/X86/pr48844-br-to-switch-vectorization.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -80,7 +80,7 @@ define dso_local void @test(ptr %start, ptr %end) #0 {
8080
; AVX2: middle.block:
8181
; AVX2-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]]
8282
; AVX2-NEXT: br i1 [[CMP_N]], label [[EXIT]], label [[BB12_PREHEADER11]]
83-
; AVX2: bb12.preheader11:
83+
; AVX2: bb12.preheader8:
8484
; AVX2-NEXT: [[PTR2_PH:%.*]] = phi ptr [ [[START]], [[BB12_PREHEADER]] ], [ [[IND_END]], [[MIDDLE_BLOCK]] ]
8585
; AVX2-NEXT: br label [[BB12:%.*]]
8686
; AVX2: bb12:

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