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[Mips] ctpop.mir - regenerate checks to improve codegen diff in #86505 
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  • llvm/test/CodeGen/Mips/GlobalISel/legalizer

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‎llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctpop.mir

Lines changed: 64 additions & 62 deletions
Original file line numberDiff line numberDiff line change
@@ -10,29 +10,30 @@ body: |
1010
1111
; MIPS32-LABEL: name: ctpop_i32
1212
; MIPS32: liveins: $a0
13-
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
14-
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
15-
; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
16-
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765
17-
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
18-
; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[AND]]
19-
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
20-
; MIPS32: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C2]](s32)
21-
; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459
22-
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
23-
; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C3]]
24-
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[AND2]]
25-
; MIPS32: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
26-
; MIPS32: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C4]](s32)
27-
; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD]]
28-
; MIPS32: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135
29-
; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C5]]
30-
; MIPS32: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009
31-
; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[C6]]
32-
; MIPS32: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
33-
; MIPS32: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C7]](s32)
34-
; MIPS32: $v0 = COPY [[LSHR3]](s32)
35-
; MIPS32: RetRA implicit $v0
13+
; MIPS32-NEXT: {{ $}}
14+
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
15+
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
16+
; MIPS32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
17+
; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765
18+
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
19+
; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[AND]]
20+
; MIPS32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
21+
; MIPS32-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C2]](s32)
22+
; MIPS32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459
23+
; MIPS32-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
24+
; MIPS32-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C3]]
25+
; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[AND2]]
26+
; MIPS32-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
27+
; MIPS32-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C4]](s32)
28+
; MIPS32-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD]]
29+
; MIPS32-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135
30+
; MIPS32-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C5]]
31+
; MIPS32-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009
32+
; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[C6]]
33+
; MIPS32-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
34+
; MIPS32-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C7]](s32)
35+
; MIPS32-NEXT: $v0 = COPY [[LSHR3]](s32)
36+
; MIPS32-NEXT: RetRA implicit $v0
3637
%0:_(s32) = COPY $a0
3738
%1:_(s32) = G_CTPOP %0(s32)
3839
$v0 = COPY %1(s32)
@@ -49,45 +50,46 @@ body: |
4950
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; MIPS32-LABEL: name: ctpop_i64
5152
; MIPS32: liveins: $a0, $a1
52-
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
53-
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
54-
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
55-
; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
56-
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765
57-
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
58-
; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[AND]]
59-
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
60-
; MIPS32: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C2]](s32)
61-
; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459
62-
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
63-
; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C3]]
64-
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[AND2]]
65-
; MIPS32: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
66-
; MIPS32: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C4]](s32)
67-
; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD]]
68-
; MIPS32: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135
69-
; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C5]]
70-
; MIPS32: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009
71-
; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[C6]]
72-
; MIPS32: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
73-
; MIPS32: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C7]](s32)
74-
; MIPS32: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
75-
; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
76-
; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[AND4]]
77-
; MIPS32: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[SUB1]], [[C2]](s32)
78-
; MIPS32: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
79-
; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SUB1]], [[C3]]
80-
; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND5]], [[AND6]]
81-
; MIPS32: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[ADD2]], [[C4]](s32)
82-
; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LSHR6]], [[ADD2]]
83-
; MIPS32: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ADD3]], [[C5]]
84-
; MIPS32: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND7]], [[C6]]
85-
; MIPS32: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[MUL1]], [[C7]](s32)
86-
; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[LSHR7]], [[LSHR3]]
87-
; MIPS32: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
88-
; MIPS32: $v0 = COPY [[ADD4]](s32)
89-
; MIPS32: $v1 = COPY [[C8]](s32)
90-
; MIPS32: RetRA implicit $v0, implicit $v1
53+
; MIPS32-NEXT: {{ $}}
54+
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
55+
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
56+
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
57+
; MIPS32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
58+
; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765
59+
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
60+
; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[AND]]
61+
; MIPS32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
62+
; MIPS32-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C2]](s32)
63+
; MIPS32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459
64+
; MIPS32-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
65+
; MIPS32-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C3]]
66+
; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[AND2]]
67+
; MIPS32-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
68+
; MIPS32-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C4]](s32)
69+
; MIPS32-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD]]
70+
; MIPS32-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135
71+
; MIPS32-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C5]]
72+
; MIPS32-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009
73+
; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[C6]]
74+
; MIPS32-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
75+
; MIPS32-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C7]](s32)
76+
; MIPS32-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
77+
; MIPS32-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
78+
; MIPS32-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[AND4]]
79+
; MIPS32-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[SUB1]], [[C2]](s32)
80+
; MIPS32-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
81+
; MIPS32-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SUB1]], [[C3]]
82+
; MIPS32-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND5]], [[AND6]]
83+
; MIPS32-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[ADD2]], [[C4]](s32)
84+
; MIPS32-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LSHR6]], [[ADD2]]
85+
; MIPS32-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ADD3]], [[C5]]
86+
; MIPS32-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND7]], [[C6]]
87+
; MIPS32-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[MUL1]], [[C7]](s32)
88+
; MIPS32-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[LSHR7]], [[LSHR3]]
89+
; MIPS32-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
90+
; MIPS32-NEXT: $v0 = COPY [[ADD4]](s32)
91+
; MIPS32-NEXT: $v1 = COPY [[C8]](s32)
92+
; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
9193
%1:_(s32) = COPY $a0
9294
%2:_(s32) = COPY $a1
9395
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)

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