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Revert "[mlir][vector] Add Vector-dialect interleave-to-shuffle pattern, enable in VectorToSPIRV" (#92006)
Reverts #91800 Reason: https://lab.llvm.org/buildbot/#/builders/268/builds/13935
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mlir/include/mlir/Dialect/Vector/TransformOps/VectorTransformOps.td

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@@ -306,20 +306,6 @@ def ApplyLowerInterleavePatternsOp : Op<Transform_Dialect,
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let assemblyFormat = "attr-dict";
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}
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def ApplyInterleaveToShufflePatternsOp : Op<Transform_Dialect,
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"apply_patterns.vector.interleave_to_shuffle",
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[DeclareOpInterfaceMethods<PatternDescriptorOpInterface>]> {
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let description = [{
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Indicates that 1D vector interleave operations should be rewritten as
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vector shuffle operations.
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This is motivated by some current codegen backends not handling vector
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interleave operations.
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}];
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let assemblyFormat = "attr-dict";
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}
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def ApplyRewriteNarrowTypePatternsOp : Op<Transform_Dialect,
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"apply_patterns.vector.rewrite_narrow_types",
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[DeclareOpInterfaceMethods<PatternDescriptorOpInterface>]> {

mlir/include/mlir/Dialect/Vector/Transforms/LoweringPatterns.h

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@@ -273,9 +273,6 @@ void populateVectorInterleaveLoweringPatterns(RewritePatternSet &patterns,
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int64_t targetRank = 1,
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PatternBenefit benefit = 1);
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void populateVectorInterleaveToShufflePatterns(RewritePatternSet &patterns,
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PatternBenefit benefit = 1);
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} // namespace vector
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} // namespace mlir
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#endif // MLIR_DIALECT_VECTOR_TRANSFORMS_LOWERINGPATTERNS_H

mlir/lib/Conversion/VectorToSPIRV/VectorToSPIRV.cpp

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@@ -18,7 +18,6 @@
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#include "mlir/Dialect/SPIRV/IR/SPIRVTypes.h"
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#include "mlir/Dialect/SPIRV/Transforms/SPIRVConversion.h"
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#include "mlir/Dialect/Vector/IR/VectorOps.h"
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#include "mlir/Dialect/Vector/Transforms/LoweringPatterns.h"
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#include "mlir/IR/Attributes.h"
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#include "mlir/IR/BuiltinAttributes.h"
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#include "mlir/IR/BuiltinTypes.h"
@@ -829,9 +828,6 @@ void mlir::populateVectorToSPIRVPatterns(SPIRVTypeConverter &typeConverter,
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// than the generic one that extracts all elements.
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patterns.add<VectorReductionToFPDotProd>(typeConverter, patterns.getContext(),
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PatternBenefit(2));
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// Need this until vector.interleave is handled.
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vector::populateVectorInterleaveToShufflePatterns(patterns);
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}
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void mlir::populateVectorReductionToSPIRVDotProductPatterns(

mlir/lib/Dialect/Vector/TransformOps/VectorTransformOps.cpp

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@@ -164,11 +164,6 @@ void transform::ApplyLowerInterleavePatternsOp::populatePatterns(
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vector::populateVectorInterleaveLoweringPatterns(patterns);
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}
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void transform::ApplyInterleaveToShufflePatternsOp::populatePatterns(
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RewritePatternSet &patterns) {
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vector::populateVectorInterleaveToShufflePatterns(patterns);
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}
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void transform::ApplyRewriteNarrowTypePatternsOp::populatePatterns(
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RewritePatternSet &patterns) {
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populateVectorNarrowTypeRewritePatterns(patterns);

mlir/lib/Dialect/Vector/Transforms/LowerVectorInterleave.cpp

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@@ -16,7 +16,6 @@
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#include "mlir/Dialect/Vector/Utils/VectorUtils.h"
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#include "mlir/IR/BuiltinTypes.h"
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#include "mlir/IR/PatternMatch.h"
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#include "mlir/Support/LogicalResult.h"
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#define DEBUG_TYPE "vector-interleave-lowering"
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@@ -78,49 +77,9 @@ class UnrollInterleaveOp : public OpRewritePattern<vector::InterleaveOp> {
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int64_t targetRank = 1;
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};
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/// Rewrite vector.interleave op into an equivalent vector.shuffle op, when
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/// applicable: `sourceType` must be 1D and non-scalable.
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///
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/// Example:
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///
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/// ```mlir
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/// vector.interleave %a, %b : vector<7xi16>
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/// ```
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///
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/// Is rewritten into:
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///
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/// ```mlir
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/// vector.shuffle %arg0, %arg1 [0, 7, 1, 8, 2, 9, 3, 10, 4, 11, 5, 12, 6, 13]
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/// : vector<7xi16>, vector<7xi16>
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/// ```
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class InterleaveToShuffle : public OpRewritePattern<vector::InterleaveOp> {
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public:
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InterleaveToShuffle(MLIRContext *context, PatternBenefit benefit = 1)
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: OpRewritePattern(context, benefit) {};
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LogicalResult matchAndRewrite(vector::InterleaveOp op,
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PatternRewriter &rewriter) const override {
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VectorType sourceType = op.getSourceVectorType();
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if (sourceType.getRank() != 1 || sourceType.isScalable()) {
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return failure();
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}
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int64_t n = sourceType.getNumElements();
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auto seq = llvm::seq<int64_t>(2 * n);
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auto zip = llvm::to_vector(llvm::map_range(
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seq, [n](int64_t i) { return (i % 2 ? n : 0) + i / 2; }));
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rewriter.replaceOpWithNewOp<ShuffleOp>(op, op.getLhs(), op.getRhs(), zip);
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return success();
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}
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};
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} // namespace
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void mlir::vector::populateVectorInterleaveLoweringPatterns(
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RewritePatternSet &patterns, int64_t targetRank, PatternBenefit benefit) {
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patterns.add<UnrollInterleaveOp>(targetRank, patterns.getContext(), benefit);
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}
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void mlir::vector::populateVectorInterleaveToShufflePatterns(
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RewritePatternSet &patterns, PatternBenefit benefit) {
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patterns.add<InterleaveToShuffle>(patterns.getContext(), benefit);
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}

mlir/test/Dialect/Vector/vector-interleave-to-shuffle.mlir

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