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[X86][NFC] Remove class (VEX/EVEX/XOP)_4V and add class VVVV
`VEX_4V` does not look simpler than `VEX, VVVV`. It's kind of confusing b/c classes like `VEX_L`, `VEX_LIG` do not imply `VEX` but it does. For APX, we have promote EVEX, NDD, NF and NDD_NF instructions. All of the 4 variants are in EVEX space and NDD/NDD_NF set the VVVV fields. To extract the common fields (e.g EVEX) into a class and set VVVV conditionally, we need VVVV to not imply other prefixes.
1 parent c03745d commit 62d8ae0

8 files changed

+509
-511
lines changed

‎llvm/lib/Target/X86/X86InstrAMX.td

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -91,19 +91,19 @@ let Predicates = [HasAMXINT8, In64BitMode] in {
9191
def TDPBSSD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
9292
(ins TILE:$src1, TILE:$src2, TILE:$src3),
9393
"tdpbssd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
94-
VEX_4V, T8XD;
94+
VEX, VVVV, T8XD;
9595
def TDPBSUD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
9696
(ins TILE:$src1, TILE:$src2, TILE:$src3),
9797
"tdpbsud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
98-
VEX_4V, T8XS;
98+
VEX, VVVV, T8XS;
9999
def TDPBUSD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
100100
(ins TILE:$src1, TILE:$src2, TILE:$src3),
101101
"tdpbusd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
102-
VEX_4V, T8PD;
102+
VEX, VVVV, T8PD;
103103
def TDPBUUD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
104104
(ins TILE:$src1, TILE:$src2, TILE:$src3),
105105
"tdpbuud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
106-
VEX_4V, T8PS;
106+
VEX, VVVV, T8PS;
107107
}
108108

109109
// Pseduo instruction for RA.
@@ -163,7 +163,7 @@ let Predicates = [HasAMXBF16, In64BitMode] in {
163163
def TDPBF16PS : I<0x5c, MRMSrcReg4VOp3, (outs TILE:$dst),
164164
(ins TILE:$src1, TILE:$src2, TILE:$src3),
165165
"tdpbf16ps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
166-
[]>, VEX_4V, T8XS;
166+
[]>, VEX, VVVV, T8XS;
167167

168168
// Pseduo instruction for RA.
169169
let isPseudo = true, Constraints = "$src4 = $dst" in
@@ -193,7 +193,7 @@ let Predicates = [HasAMXFP16, In64BitMode] in {
193193
def TDPFP16PS : I<0x5c, MRMSrcReg4VOp3, (outs TILE:$dst),
194194
(ins TILE:$src1, TILE:$src2, TILE:$src3),
195195
"tdpfp16ps\t{$src3, $src2, $src1|$src1, $src2, $src3}",
196-
[]>, VEX_4V, T8XD;
196+
[]>, VEX, VVVV, T8XD;
197197
}
198198

199199
// Pseduo instruction for RA.
@@ -222,11 +222,11 @@ let Predicates = [HasAMXCOMPLEX, In64BitMode] in {
222222
def TCMMIMFP16PS : I<0x6c, MRMSrcReg4VOp3, (outs TILE:$dst),
223223
(ins TILE:$src1, TILE:$src2, TILE:$src3),
224224
"tcmmimfp16ps\t{$src3, $src2, $src1|$src1, $src2, $src3}",
225-
[]>, T8PD, VEX_4V;
225+
[]>, T8PD, VEX, VVVV;
226226
def TCMMRLFP16PS : I<0x6c, MRMSrcReg4VOp3, (outs TILE:$dst),
227227
(ins TILE:$src1, TILE:$src2, TILE:$src3),
228228
"tcmmrlfp16ps\t{$src3, $src2, $src1|$src1, $src2, $src3}",
229-
[]>, VEX_4V, WIG, T8PS;
229+
[]>, VEX, VVVV, WIG, T8PS;
230230

231231
} // Constraints = "$src1 = $dst"
232232

‎llvm/lib/Target/X86/X86InstrAVX512.td

Lines changed: 223 additions & 223 deletions
Large diffs are not rendered by default.

‎llvm/lib/Target/X86/X86InstrArithmetic.td

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1095,23 +1095,23 @@ let Predicates = [HasBMI, NoEGPR] in {
10951095
def rr : I<0xF2, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
10961096
!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
10971097
[(set RC:$dst, EFLAGS, (X86and_flag (not RC:$src1), RC:$src2))]>,
1098-
VEX_4V, Sched<[sched]>;
1098+
VEX, VVVV, Sched<[sched]>;
10991099
def rm : I<0xF2, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
11001100
!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
11011101
[(set RC:$dst, EFLAGS,
11021102
(X86and_flag (not RC:$src1), (ld_frag addr:$src2)))]>,
1103-
VEX_4V, Sched<[sched.Folded, sched.ReadAfterFold]>;
1103+
VEX, VVVV, Sched<[sched.Folded, sched.ReadAfterFold]>;
11041104
}
11051105
let Predicates = [HasBMI, HasEGPR, In64BitMode] in {
11061106
def rr_EVEX : I<0xF2, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
11071107
!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
11081108
[(set RC:$dst, EFLAGS, (X86and_flag (not RC:$src1), RC:$src2))]>,
1109-
EVEX_4V, Sched<[sched]>;
1109+
EVEX, VVVV, Sched<[sched]>;
11101110
def rm_EVEX : I<0xF2, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
11111111
!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
11121112
[(set RC:$dst, EFLAGS,
11131113
(X86and_flag (not RC:$src1), (ld_frag addr:$src2)))]>,
1114-
EVEX_4V, Sched<[sched.Folded, sched.ReadAfterFold]>;
1114+
EVEX, VVVV, Sched<[sched.Folded, sched.ReadAfterFold]>;
11151115
}
11161116
}
11171117

@@ -1141,12 +1141,12 @@ let hasSideEffects = 0 in {
11411141
let Predicates = [HasBMI2, NoEGPR] in {
11421142
def rr : I<0xF6, MRMSrcReg, (outs RC:$dst1, RC:$dst2), (ins RC:$src),
11431143
!strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"),
1144-
[]>, T8XD, VEX_4V, Sched<[WriteIMulH, sched]>;
1144+
[]>, T8XD, VEX, VVVV, Sched<[WriteIMulH, sched]>;
11451145

11461146
let mayLoad = 1 in
11471147
def rm : I<0xF6, MRMSrcMem, (outs RC:$dst1, RC:$dst2), (ins x86memop:$src),
11481148
!strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"),
1149-
[]>, T8XD, VEX_4V,
1149+
[]>, T8XD, VEX, VVVV,
11501150
Sched<[WriteIMulHLd, sched.Folded,
11511151
// Memory operand.
11521152
ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault,
@@ -1165,11 +1165,11 @@ let Predicates = [HasBMI2, NoEGPR] in {
11651165
let Predicates = [HasBMI2, HasEGPR, In64BitMode] in
11661166
def rr#_EVEX : I<0xF6, MRMSrcReg, (outs RC:$dst1, RC:$dst2), (ins RC:$src),
11671167
!strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"),
1168-
[]>, T8XD, EVEX_4V, Sched<[WriteIMulH, sched]>;
1168+
[]>, T8XD, EVEX, VVVV, Sched<[WriteIMulH, sched]>;
11691169
let Predicates = [HasBMI2, HasEGPR, In64BitMode], mayLoad = 1 in
11701170
def rm#_EVEX : I<0xF6, MRMSrcMem, (outs RC:$dst1, RC:$dst2), (ins x86memop:$src),
11711171
!strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"),
1172-
[]>, T8XD, EVEX_4V,
1172+
[]>, T8XD, EVEX, VVVV,
11731173
Sched<[WriteIMulHLd, sched.Folded,
11741174
// Memory operand.
11751175
ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault,

‎llvm/lib/Target/X86/X86InstrMisc.td

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -165,10 +165,10 @@ def POPP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "popp\t$reg", []>,
165165
REX_W, ExplicitREX2Prefix, Requires<[In64BitMode]>;
166166
def POP2: I<0x8F, MRM0r, (outs GR64:$reg1, GR64:$reg2), (ins),
167167
"pop2\t{$reg2, $reg1|$reg1, $reg2}",
168-
[]>, EVEX_4V, EVEX_B, T_MAP4PS;
168+
[]>, EVEX, VVVV, EVEX_B, T_MAP4PS;
169169
def POP2P: I<0x8F, MRM0r, (outs GR64:$reg1, GR64:$reg2), (ins),
170170
"pop2p\t{$reg2, $reg1|$reg1, $reg2}",
171-
[]>, EVEX_4V, EVEX_B, T_MAP4PS, REX_W;
171+
[]>, EVEX, VVVV, EVEX_B, T_MAP4PS, REX_W;
172172

173173
} // mayLoad, SchedRW
174174
let mayLoad = 1, mayStore = 1, SchedRW = [WriteCopy] in
@@ -186,10 +186,10 @@ def PUSHP64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "pushp\t$reg", []>,
186186
REX_W, ExplicitREX2Prefix, Requires<[In64BitMode]>;
187187
def PUSH2: I<0xFF, MRM6r, (outs), (ins GR64:$reg1, GR64:$reg2),
188188
"push2\t{$reg2, $reg1|$reg1, $reg2}",
189-
[]>, EVEX_4V, EVEX_B, T_MAP4PS;
189+
[]>, EVEX, VVVV, EVEX_B, T_MAP4PS;
190190
def PUSH2P: I<0xFF, MRM6r, (outs), (ins GR64:$reg1, GR64:$reg2),
191191
"push2p\t{$reg2, $reg1|$reg1, $reg2}",
192-
[]>, EVEX_4V, EVEX_B, T_MAP4PS, REX_W;
192+
[]>, EVEX, VVVV, EVEX_B, T_MAP4PS, REX_W;
193193
} // mayStore, SchedRW
194194
let mayLoad = 1, mayStore = 1, SchedRW = [WriteCopy] in {
195195
def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>,
@@ -1218,11 +1218,11 @@ multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
12181218
let hasSideEffects = 0 in {
12191219
def rr#Suffix : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
12201220
!strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>,
1221-
T8PS, VEX_4V, Sched<[sched]>;
1221+
T8PS, VEX, VVVV, Sched<[sched]>;
12221222
let mayLoad = 1 in
12231223
def rm#Suffix : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
12241224
!strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>,
1225-
T8PS, VEX_4V, Sched<[sched.Folded]>;
1225+
T8PS, VEX, VVVV, Sched<[sched.Folded]>;
12261226
}
12271227
}
12281228

@@ -1371,11 +1371,11 @@ multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
13711371
def rr#Suffix : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
13721372
!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
13731373
[(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>,
1374-
VEX_4V, Sched<[WriteALU]>;
1374+
VEX, VVVV, Sched<[WriteALU]>;
13751375
def rm#Suffix : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
13761376
!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
13771377
[(set RC:$dst, (OpNode RC:$src1, (ld_frag addr:$src2)))]>,
1378-
VEX_4V, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>;
1378+
VEX, VVVV, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>;
13791379
}
13801380

13811381
let Predicates = [HasBMI2, NoEGPR] in {
@@ -1419,12 +1419,12 @@ multiclass lwpins_intr<RegisterClass RC> {
14191419
def rri : Ii32<0x12, MRM0r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl),
14201420
"lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}",
14211421
[(set EFLAGS, (X86lwpins RC:$src0, GR32:$src1, timm:$cntl))]>,
1422-
XOP_4V, XOPA;
1422+
XOP, VVVV, XOPA;
14231423
let mayLoad = 1 in
14241424
def rmi : Ii32<0x12, MRM0m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl),
14251425
"lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}",
14261426
[(set EFLAGS, (X86lwpins RC:$src0, (loadi32 addr:$src1), timm:$cntl))]>,
1427-
XOP_4V, XOPA;
1427+
XOP, VVVV, XOPA;
14281428
}
14291429

14301430
let Defs = [EFLAGS] in {
@@ -1435,12 +1435,12 @@ let Defs = [EFLAGS] in {
14351435
multiclass lwpval_intr<RegisterClass RC, Intrinsic Int> {
14361436
def rri : Ii32<0x12, MRM1r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl),
14371437
"lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}",
1438-
[(Int RC:$src0, GR32:$src1, timm:$cntl)]>, XOP_4V, XOPA;
1438+
[(Int RC:$src0, GR32:$src1, timm:$cntl)]>, XOP, VVVV, XOPA;
14391439
let mayLoad = 1 in
14401440
def rmi : Ii32<0x12, MRM1m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl),
14411441
"lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}",
14421442
[(Int RC:$src0, (loadi32 addr:$src1), timm:$cntl)]>,
1443-
XOP_4V, XOPA;
1443+
XOP, VVVV, XOPA;
14441444
}
14451445

14461446
defm LWPVAL32 : lwpval_intr<GR32, int_x86_lwpval32>;
@@ -1670,14 +1670,14 @@ def CMPCCXADDmr32 : I<0xe0, MRMDestMem4VOp3CC, (outs GR32:$dst),
16701670
"cmp${cond}xadd\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}",
16711671
[(set GR32:$dst, (X86cmpccxadd addr:$dstsrc2,
16721672
GR32:$dstsrc1, GR32:$src3, timm:$cond))]>,
1673-
VEX_4V, T8PD, Sched<[WriteXCHG]>;
1673+
VEX, VVVV, T8PD, Sched<[WriteXCHG]>;
16741674

16751675
def CMPCCXADDmr64 : I<0xe0, MRMDestMem4VOp3CC, (outs GR64:$dst),
16761676
(ins GR64:$dstsrc1, i64mem:$dstsrc2, GR64:$src3, ccode:$cond),
16771677
"cmp${cond}xadd\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}",
16781678
[(set GR64:$dst, (X86cmpccxadd addr:$dstsrc2,
16791679
GR64:$dstsrc1, GR64:$src3, timm:$cond))]>,
1680-
VEX_4V, REX_W, T8PD, Sched<[WriteXCHG]>;
1680+
VEX, VVVV, REX_W, T8PD, Sched<[WriteXCHG]>;
16811681
}
16821682

16831683
//===----------------------------------------------------------------------===//

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