[ValueTypes] Add v1 to v12 vector type support for i1, i8, i16, f16, i64, f64

This patch is a preliminary step to prepare RISC-V for supporting more VLS type
code generation. The currently affected targets are x86, AArch64, and AMDGPU:

- x86: The code generation order and register usage are different, but the
       generated instructions remain the same.

- AArch64: There is a slight change in a GlobalISel dump.

- AMDGPU: TruncStore from MVT::v5i32 to MVT::v5i8 was previously illegal
          because MVT::v5i8 did not exist. Now, it must be explicitly declared
          as Expand. Additionally, the calling convention need to correctly
          handle the newly added non-power-of-2 vector types.

Author: kito-cheng