Skip to content

Commit 6325dd5

Browse files
authored
[HLSL][SPIR-V] Add SV_DispatchThreadID semantic support (#82536)
Add SPIR-V backend support for the HLSL SV_DispatchThreadID semantic attribute, which is lowered to a @llvm.dx.thread.id intrinsic in LLVM IR. In the SPIR-V backend, this is now correctly translated to a `GlobalInvocationId` builtin variable. Fixes #82534
1 parent aec6a04 commit 6325dd5

File tree

6 files changed

+178
-22
lines changed

6 files changed

+178
-22
lines changed

clang/lib/CodeGen/CGHLSLRuntime.cpp

Lines changed: 14 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,7 @@
1818
#include "clang/AST/Decl.h"
1919
#include "clang/Basic/TargetOptions.h"
2020
#include "llvm/IR/IntrinsicsDirectX.h"
21+
#include "llvm/IR/IntrinsicsSPIRV.h"
2122
#include "llvm/IR/Metadata.h"
2223
#include "llvm/IR/Module.h"
2324
#include "llvm/Support/FormatVariadic.h"
@@ -342,8 +343,19 @@ llvm::Value *CGHLSLRuntime::emitInputSemantic(IRBuilder<> &B,
342343
return B.CreateCall(FunctionCallee(DxGroupIndex));
343344
}
344345
if (D.hasAttr<HLSLSV_DispatchThreadIDAttr>()) {
345-
llvm::Function *DxThreadID = CGM.getIntrinsic(Intrinsic::dx_thread_id);
346-
return buildVectorInput(B, DxThreadID, Ty);
346+
llvm::Function *ThreadIDIntrinsic;
347+
switch (CGM.getTarget().getTriple().getArch()) {
348+
case llvm::Triple::dxil:
349+
ThreadIDIntrinsic = CGM.getIntrinsic(Intrinsic::dx_thread_id);
350+
break;
351+
case llvm::Triple::spirv:
352+
ThreadIDIntrinsic = CGM.getIntrinsic(Intrinsic::spv_thread_id);
353+
break;
354+
default:
355+
llvm_unreachable("Input semantic not supported by target");
356+
break;
357+
}
358+
return buildVectorInput(B, ThreadIDIntrinsic, Ty);
347359
}
348360
assert(false && "Unhandled parameter attribute");
349361
return nullptr;
Lines changed: 16 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1,28 +1,25 @@
1-
// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.3-library -x hlsl -emit-llvm -finclude-default-header -disable-llvm-passes -o - %s
1+
// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.3-library -x hlsl -emit-llvm -finclude-default-header -disable-llvm-passes -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-DXIL
2+
// RUN: %clang_cc1 -triple spirv-linux-vulkan-library -x hlsl -emit-llvm -finclude-default-header -disable-llvm-passes -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-SPIRV
23

34
// Make sure SV_DispatchThreadID translated into dx.thread.id.
45

5-
const RWBuffer<float> In;
6-
RWBuffer<float> Out;
7-
8-
// CHECK: define void @foo()
9-
// CHECK: %[[ID:[0-9a-zA-Z]+]] = call i32 @llvm.dx.thread.id(i32 0)
10-
// CHECK: call void @"?foo@@YAXH@Z"(i32 %[[ID]])
6+
// CHECK: define void @foo()
7+
// CHECK-DXIL: %[[#ID:]] = call i32 @llvm.dx.thread.id(i32 0)
8+
// CHECK-SPIRV: %[[#ID:]] = call i32 @llvm.spv.thread.id(i32 0)
9+
// CHECK: call void @{{.*}}foo{{.*}}(i32 %[[#ID]])
1110
[shader("compute")]
1211
[numthreads(8,8,1)]
13-
void foo(uint Idx : SV_DispatchThreadID) {
14-
Out[Idx] = In[Idx];
15-
}
12+
void foo(uint Idx : SV_DispatchThreadID) {}
1613

17-
// CHECK: define void @bar()
18-
// CHECK: %[[ID_X:[0-9a-zA-Z]+]] = call i32 @llvm.dx.thread.id(i32 0)
19-
// CHECK: %[[ID_X_:[0-9a-zA-Z]+]] = insertelement <2 x i32> poison, i32 %[[ID_X]], i64 0
20-
// CHECK: %[[ID_Y:[0-9a-zA-Z]+]] = call i32 @llvm.dx.thread.id(i32 1)
21-
// CHECK: %[[ID_XY:[0-9a-zA-Z]+]] = insertelement <2 x i32> %[[ID_X_]], i32 %[[ID_Y]], i64 1
22-
// CHECK: call void @"?bar@@YAXT?$__vector@H$01@__clang@@@Z"(<2 x i32> %[[ID_XY]])
14+
// CHECK: define void @bar()
15+
// CHECK-DXIL: %[[#ID_X:]] = call i32 @llvm.dx.thread.id(i32 0)
16+
// CHECK-SPIRV: %[[#ID_X:]] = call i32 @llvm.spv.thread.id(i32 0)
17+
// CHECK: %[[#ID_X_:]] = insertelement <2 x i32> poison, i32 %[[#ID_X]], i64 0
18+
// CHECK-DXIL: %[[#ID_Y:]] = call i32 @llvm.dx.thread.id(i32 1)
19+
// CHECK-SPIRV: %[[#ID_Y:]] = call i32 @llvm.spv.thread.id(i32 1)
20+
// CHECK: %[[#ID_XY:]] = insertelement <2 x i32> %[[#ID_X_]], i32 %[[#ID_Y]], i64 1
21+
// CHECK-DXIL: call void @{{.*}}bar{{.*}}(<2 x i32> %[[#ID_XY]])
2322
[shader("compute")]
2423
[numthreads(8,8,1)]
25-
void bar(uint2 Idx : SV_DispatchThreadID) {
26-
Out[Idx.y] = In[Idx.x];
27-
}
24+
void bar(uint2 Idx : SV_DispatchThreadID) {}
2825

llvm/include/llvm/IR/IntrinsicsSPIRV.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,7 @@ let TargetPrefix = "spv" in {
4141
def int_spv_expect : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>;
4242

4343
// The following intrinsic(s) are mirrored from IntrinsicsDirectX.td for HLSL support.
44+
def int_spv_thread_id : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem, IntrWillReturn]>;
4445
def int_spv_create_handle : ClangBuiltin<"__builtin_hlsl_create_handle">,
4546
Intrinsic<[ llvm_ptr_ty ], [llvm_i8_ty], [IntrWillReturn]>;
4647
}

llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -525,7 +525,9 @@ Register SPIRVGlobalRegistry::buildGlobalVariable(
525525

526526
// Output decorations for the GV.
527527
// TODO: maybe move to GenerateDecorations pass.
528-
if (IsConst)
528+
const SPIRVSubtarget &ST =
529+
cast<SPIRVSubtarget>(MIRBuilder.getMF().getSubtarget());
530+
if (IsConst && ST.isOpenCLEnv())
529531
buildOpDecorate(Reg, MIRBuilder, SPIRV::Decoration::Constant, {});
530532

531533
if (GVar && GVar->getAlign().valueOrOne().value() != 1) {

llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

Lines changed: 68 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -194,6 +194,9 @@ class SPIRVInstructionSelector : public InstructionSelector {
194194
bool selectLog10(Register ResVReg, const SPIRVType *ResType,
195195
MachineInstr &I) const;
196196

197+
bool selectSpvThreadId(Register ResVReg, const SPIRVType *ResType,
198+
MachineInstr &I) const;
199+
197200
bool selectUnmergeValues(MachineInstr &I) const;
198201

199202
Register buildI32Constant(uint32_t Val, MachineInstr &I,
@@ -301,6 +304,7 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg,
301304
case TargetOpcode::G_FREEZE:
302305
return selectFreeze(ResVReg, ResType, I);
303306

307+
case TargetOpcode::G_INTRINSIC:
304308
case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
305309
case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS:
306310
return selectIntrinsic(ResVReg, ResType, I);
@@ -1614,6 +1618,8 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
16141618
.addUse(I.getOperand(2).getReg())
16151619
.addUse(I.getOperand(3).getReg());
16161620
break;
1621+
case Intrinsic::spv_thread_id:
1622+
return selectSpvThreadId(ResVReg, ResType, I);
16171623
default:
16181624
llvm_unreachable("Intrinsic selection not implemented");
16191625
}
@@ -1864,6 +1870,68 @@ bool SPIRVInstructionSelector::selectLog10(Register ResVReg,
18641870
return Result;
18651871
}
18661872

1873+
bool SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg,
1874+
const SPIRVType *ResType,
1875+
MachineInstr &I) const {
1876+
// DX intrinsic: @llvm.dx.thread.id(i32)
1877+
// ID Name Description
1878+
// 93 ThreadId reads the thread ID
1879+
1880+
MachineIRBuilder MIRBuilder(I);
1881+
const SPIRVType *U32Type = GR.getOrCreateSPIRVIntegerType(32, MIRBuilder);
1882+
const SPIRVType *Vec3Ty =
1883+
GR.getOrCreateSPIRVVectorType(U32Type, 3, MIRBuilder);
1884+
const SPIRVType *PtrType = GR.getOrCreateSPIRVPointerType(
1885+
Vec3Ty, MIRBuilder, SPIRV::StorageClass::Input);
1886+
1887+
// Create new register for GlobalInvocationID builtin variable.
1888+
Register NewRegister =
1889+
MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::IDRegClass);
1890+
MIRBuilder.getMRI()->setType(NewRegister, LLT::pointer(0, 32));
1891+
GR.assignSPIRVTypeToVReg(PtrType, NewRegister, MIRBuilder.getMF());
1892+
1893+
// Build GlobalInvocationID global variable with the necessary decorations.
1894+
Register Variable = GR.buildGlobalVariable(
1895+
NewRegister, PtrType,
1896+
getLinkStringForBuiltIn(SPIRV::BuiltIn::GlobalInvocationId), nullptr,
1897+
SPIRV::StorageClass::Input, nullptr, true, true,
1898+
SPIRV::LinkageType::Import, MIRBuilder, false);
1899+
1900+
// Create new register for loading value.
1901+
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
1902+
Register LoadedRegister = MRI->createVirtualRegister(&SPIRV::IDRegClass);
1903+
MIRBuilder.getMRI()->setType(LoadedRegister, LLT::pointer(0, 32));
1904+
GR.assignSPIRVTypeToVReg(Vec3Ty, LoadedRegister, MIRBuilder.getMF());
1905+
1906+
// Load v3uint value from the global variable.
1907+
BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpLoad))
1908+
.addDef(LoadedRegister)
1909+
.addUse(GR.getSPIRVTypeID(Vec3Ty))
1910+
.addUse(Variable);
1911+
1912+
// Get Thread ID index. Expecting operand is a constant immediate value,
1913+
// wrapped in a type assignment.
1914+
assert(I.getOperand(2).isReg());
1915+
Register ThreadIdReg = I.getOperand(2).getReg();
1916+
SPIRVType *ConstTy = this->MRI->getVRegDef(ThreadIdReg);
1917+
assert(ConstTy && ConstTy->getOpcode() == SPIRV::ASSIGN_TYPE &&
1918+
ConstTy->getOperand(1).isReg());
1919+
Register ConstReg = ConstTy->getOperand(1).getReg();
1920+
const MachineInstr *Const = this->MRI->getVRegDef(ConstReg);
1921+
assert(Const && Const->getOpcode() == TargetOpcode::G_CONSTANT);
1922+
const llvm::APInt &Val = Const->getOperand(1).getCImm()->getValue();
1923+
const uint32_t ThreadId = Val.getZExtValue();
1924+
1925+
// Extract the thread ID from the loaded vector value.
1926+
MachineBasicBlock &BB = *I.getParent();
1927+
auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract))
1928+
.addDef(ResVReg)
1929+
.addUse(GR.getSPIRVTypeID(ResType))
1930+
.addUse(LoadedRegister)
1931+
.addImm(ThreadId);
1932+
return MIB.constrainAllUses(TII, TRI, RBI);
1933+
}
1934+
18671935
namespace llvm {
18681936
InstructionSelector *
18691937
createSPIRVInstructionSelector(const SPIRVTargetMachine &TM,
Lines changed: 76 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,76 @@
1+
; RUN: llc -O0 -mtriple=spirv-vulkan-unknown %s -o - | FileCheck %s
2+
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o - -filetype=obj | spirv-val %}
3+
4+
; This file generated from the following command:
5+
; clang -cc1 -triple spirv-vulkan-library -x hlsl -emit-llvm -disable-llvm-passes -finclude-default-header - -o - <<EOF
6+
; [shader("compute")]
7+
; [numthreads(1,1,1)]
8+
; void main(uint3 ID : SV_DispatchThreadID) {}
9+
; EOF
10+
11+
; CHECK-DAG: %[[#int:]] = OpTypeInt 32 0
12+
; CHECK-DAG: %[[#v3int:]] = OpTypeVector %[[#int]] 3
13+
; CHECK-DAG: %[[#ptr_Input_v3int:]] = OpTypePointer Input %[[#v3int]]
14+
; CHECK-DAG: %[[#tempvar:]] = OpUndef %[[#v3int]]
15+
; CHECK-DAG: %[[#GlobalInvocationId:]] = OpVariable %[[#ptr_Input_v3int]] Input
16+
17+
; CHECK-DAG: OpEntryPoint GLCompute {{.*}} %[[#GlobalInvocationId]]
18+
; CHECK-DAG: OpName %[[#GlobalInvocationId]] "__spirv_BuiltInGlobalInvocationId"
19+
; CHECK-DAG: OpDecorate %[[#GlobalInvocationId]] LinkageAttributes "__spirv_BuiltInGlobalInvocationId" Import
20+
; CHECK-DAG: OpDecorate %[[#GlobalInvocationId]] BuiltIn GlobalInvocationId
21+
22+
; ModuleID = '-'
23+
source_filename = "-"
24+
target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
25+
target triple = "spirv-unknown-vulkan-library"
26+
27+
; Function Attrs: noinline norecurse nounwind optnone
28+
define internal spir_func void @main(<3 x i32> noundef %ID) #0 {
29+
entry:
30+
%ID.addr = alloca <3 x i32>, align 16
31+
store <3 x i32> %ID, ptr %ID.addr, align 16
32+
ret void
33+
}
34+
35+
; Function Attrs: norecurse
36+
define void @main.1() #1 {
37+
entry:
38+
39+
; CHECK: %[[#load:]] = OpLoad %[[#v3int]] %[[#GlobalInvocationId]]
40+
; CHECK: %[[#load0:]] = OpCompositeExtract %[[#int]] %[[#load]] 0
41+
%0 = call i32 @llvm.spv.thread.id(i32 0)
42+
43+
; CHECK: %[[#tempvar:]] = OpCompositeInsert %[[#v3int]] %[[#load0]] %[[#tempvar]] 0
44+
%1 = insertelement <3 x i32> poison, i32 %0, i64 0
45+
46+
; CHECK: %[[#load:]] = OpLoad %[[#v3int]] %[[#GlobalInvocationId]]
47+
; CHECK: %[[#load1:]] = OpCompositeExtract %[[#int]] %[[#load]] 1
48+
%2 = call i32 @llvm.spv.thread.id(i32 1)
49+
50+
; CHECK: %[[#tempvar:]] = OpCompositeInsert %[[#v3int]] %[[#load1]] %[[#tempvar]] 1
51+
%3 = insertelement <3 x i32> %1, i32 %2, i64 1
52+
53+
; CHECK: %[[#load:]] = OpLoad %[[#v3int]] %[[#GlobalInvocationId]]
54+
; CHECK: %[[#load2:]] = OpCompositeExtract %[[#int]] %[[#load]] 2
55+
%4 = call i32 @llvm.spv.thread.id(i32 2)
56+
57+
; CHECK: %[[#tempvar:]] = OpCompositeInsert %[[#v3int]] %[[#load2]] %[[#tempvar]] 2
58+
%5 = insertelement <3 x i32> %3, i32 %4, i64 2
59+
60+
call void @main(<3 x i32> %5)
61+
ret void
62+
}
63+
64+
; Function Attrs: nounwind willreturn memory(none)
65+
declare i32 @llvm.spv.thread.id(i32) #2
66+
67+
attributes #0 = { noinline norecurse nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
68+
attributes #1 = { norecurse "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
69+
attributes #2 = { nounwind willreturn memory(none) }
70+
71+
!llvm.module.flags = !{!0, !1}
72+
!llvm.ident = !{!2}
73+
74+
!0 = !{i32 1, !"wchar_size", i32 4}
75+
!1 = !{i32 4, !"dx.disable_optimizations", i32 1}
76+
!2 = !{!"clang version 19.0.0git ([email protected]:llvm/llvm-project.git 91600507765679e92434ec7c5edb883bf01f847f)"}

0 commit comments

Comments
 (0)