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[RISCV] Use the store value's VT as the MemoryVT after combining riscv.masked.strided.store (#89874)
According to `RISCVTargetLowering::getTgtMemIntrinsic`, the MemoryVT is the scalar element VT for strided store and the MemoryVT is the same as the store value's VT for unit-stride store. After combining `riscv.masked.strided.store` to `masked.store`, we just use the scalar element VT to construct `masked.store`, which is wrong. With wrong MemoryVT, the DAGCombiner will combine `trunc+masked.store` to truncated `masked.store` because `TLI.canCombineTruncStore` returns true. So, we should use the store value's VT as the MemoryVT. This fixes #89833.
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llvm/lib/Target/RISCV/RISCVISelLowering.cpp

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@@ -16832,7 +16832,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
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StrideC && StrideC->getZExtValue() == ElementSize)
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return DAG.getMaskedStore(Store->getChain(), DL, Value, Base,
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DAG.getUNDEF(XLenVT), Mask,
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Store->getMemoryVT(), Store->getMemOperand(),
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Value.getValueType(), Store->getMemOperand(),
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ISD::UNINDEXED, false);
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return SDValue();
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}

llvm/test/CodeGen/RISCV/pr89833.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s
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declare void @llvm.riscv.masked.strided.store.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr, i64, <vscale x 16 x i1>)
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define void @test(<vscale x 16 x i16> %value, <vscale x 16 x i1> %mask) {
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; CHECK-LABEL: test:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
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; CHECK-NEXT: vnsrl.wi v12, v8, 0
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; CHECK-NEXT: vse8.v v12, (zero), v0.t
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; CHECK-NEXT: ret
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%trunc = trunc <vscale x 16 x i16> %value to <vscale x 16 x i8>
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call void @llvm.riscv.masked.strided.store.nxv16i8.p0.i64(<vscale x 16 x i8> %trunc, ptr null, i64 1, <vscale x 16 x i1> %mask)
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ret void
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}

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