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Revert "[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buffer.*.pN (#110714)"
Some builders has been failing tests. ``` Failed Tests (2): LLVM :: CodeGen/AMDGPU/GlobalISel/inst-select-load-global-old-legalization.mir LLVM :: CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir ``` This reverts commit ae5bd2a. (llvmorg-20-init-7805-gae5bd2a9f292)
1 parent a2994de commit 650c41a

12 files changed

+263
-3980
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

+19-42
Original file line numberDiff line numberDiff line change
@@ -494,8 +494,6 @@ static bool loadStoreBitcastWorkaround(const LLT Ty) {
494494
return false;
495495

496496
const unsigned Size = Ty.getSizeInBits();
497-
if (Ty.isPointerVector())
498-
return true;
499497
if (Size <= 64)
500498
return false;
501499
// Address space 8 pointers get their own workaround.
@@ -504,6 +502,9 @@ static bool loadStoreBitcastWorkaround(const LLT Ty) {
504502
if (!Ty.isVector())
505503
return true;
506504

505+
if (Ty.isPointerVector())
506+
return true;
507+
507508
unsigned EltSize = Ty.getScalarSizeInBits();
508509
return EltSize != 32 && EltSize != 64;
509510
}
@@ -5793,9 +5794,8 @@ Register AMDGPULegalizerInfo::handleD16VData(MachineIRBuilder &B,
57935794
return Reg;
57945795
}
57955796

5796-
Register AMDGPULegalizerInfo::fixStoreSourceType(MachineIRBuilder &B,
5797-
Register VData, LLT MemTy,
5798-
bool IsFormat) const {
5797+
Register AMDGPULegalizerInfo::fixStoreSourceType(
5798+
MachineIRBuilder &B, Register VData, bool IsFormat) const {
57995799
MachineRegisterInfo *MRI = B.getMRI();
58005800
LLT Ty = MRI->getType(VData);
58015801

@@ -5805,10 +5805,6 @@ Register AMDGPULegalizerInfo::fixStoreSourceType(MachineIRBuilder &B,
58055805
if (hasBufferRsrcWorkaround(Ty))
58065806
return castBufferRsrcToV4I32(VData, B);
58075807

5808-
if (shouldBitcastLoadStoreType(ST, Ty, MemTy)) {
5809-
Ty = getBitcastRegisterType(Ty);
5810-
VData = B.buildBitcast(Ty, VData).getReg(0);
5811-
}
58125808
// Fixup illegal register types for i8 stores.
58135809
if (Ty == LLT::scalar(8) || Ty == S16) {
58145810
Register AnyExt = B.buildAnyExt(LLT::scalar(32), VData).getReg(0);
@@ -5826,27 +5822,23 @@ Register AMDGPULegalizerInfo::fixStoreSourceType(MachineIRBuilder &B,
58265822
}
58275823

58285824
bool AMDGPULegalizerInfo::legalizeBufferStore(MachineInstr &MI,
5829-
LegalizerHelper &Helper,
5825+
MachineRegisterInfo &MRI,
5826+
MachineIRBuilder &B,
58305827
bool IsTyped,
58315828
bool IsFormat) const {
5832-
MachineIRBuilder &B = Helper.MIRBuilder;
5833-
MachineRegisterInfo &MRI = *B.getMRI();
5834-
58355829
Register VData = MI.getOperand(1).getReg();
58365830
LLT Ty = MRI.getType(VData);
58375831
LLT EltTy = Ty.getScalarType();
58385832
const bool IsD16 = IsFormat && (EltTy.getSizeInBits() == 16);
58395833
const LLT S32 = LLT::scalar(32);
58405834

5841-
MachineMemOperand *MMO = *MI.memoperands_begin();
5842-
const int MemSize = MMO->getSize().getValue();
5843-
LLT MemTy = MMO->getMemoryType();
5844-
5845-
VData = fixStoreSourceType(B, VData, MemTy, IsFormat);
5846-
5835+
VData = fixStoreSourceType(B, VData, IsFormat);
58475836
castBufferRsrcArgToV4I32(MI, B, 2);
58485837
Register RSrc = MI.getOperand(2).getReg();
58495838

5839+
MachineMemOperand *MMO = *MI.memoperands_begin();
5840+
const int MemSize = MMO->getSize().getValue();
5841+
58505842
unsigned ImmOffset;
58515843

58525844
// The typed intrinsics add an immediate after the registers.
@@ -5938,13 +5930,10 @@ static void buildBufferLoad(unsigned Opc, Register LoadDstReg, Register RSrc,
59385930
}
59395931

59405932
bool AMDGPULegalizerInfo::legalizeBufferLoad(MachineInstr &MI,
5941-
LegalizerHelper &Helper,
5933+
MachineRegisterInfo &MRI,
5934+
MachineIRBuilder &B,
59425935
bool IsFormat,
59435936
bool IsTyped) const {
5944-
MachineIRBuilder &B = Helper.MIRBuilder;
5945-
MachineRegisterInfo &MRI = *B.getMRI();
5946-
GISelChangeObserver &Observer = Helper.Observer;
5947-
59485937
// FIXME: Verifier should enforce 1 MMO for these intrinsics.
59495938
MachineMemOperand *MMO = *MI.memoperands_begin();
59505939
const LLT MemTy = MMO->getMemoryType();
@@ -5993,21 +5982,9 @@ bool AMDGPULegalizerInfo::legalizeBufferLoad(MachineInstr &MI,
59935982
// Make addrspace 8 pointers loads into 4xs32 loads here, so the rest of the
59945983
// logic doesn't have to handle that case.
59955984
if (hasBufferRsrcWorkaround(Ty)) {
5996-
Observer.changingInstr(MI);
59975985
Ty = castBufferRsrcFromV4I32(MI, B, MRI, 0);
5998-
Observer.changedInstr(MI);
59995986
Dst = MI.getOperand(0).getReg();
6000-
B.setInsertPt(B.getMBB(), MI);
60015987
}
6002-
if (shouldBitcastLoadStoreType(ST, Ty, MemTy)) {
6003-
Ty = getBitcastRegisterType(Ty);
6004-
Observer.changingInstr(MI);
6005-
Helper.bitcastDst(MI, Ty, 0);
6006-
Observer.changedInstr(MI);
6007-
Dst = MI.getOperand(0).getReg();
6008-
B.setInsertPt(B.getMBB(), MI);
6009-
}
6010-
60115988
LLT EltTy = Ty.getScalarType();
60125989
const bool IsD16 = IsFormat && (EltTy.getSizeInBits() == 16);
60135990
const bool Unpacked = ST.hasUnpackedD16VMem();
@@ -7387,17 +7364,17 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
73877364
case Intrinsic::amdgcn_raw_ptr_buffer_store:
73887365
case Intrinsic::amdgcn_struct_buffer_store:
73897366
case Intrinsic::amdgcn_struct_ptr_buffer_store:
7390-
return legalizeBufferStore(MI, Helper, false, false);
7367+
return legalizeBufferStore(MI, MRI, B, false, false);
73917368
case Intrinsic::amdgcn_raw_buffer_store_format:
73927369
case Intrinsic::amdgcn_raw_ptr_buffer_store_format:
73937370
case Intrinsic::amdgcn_struct_buffer_store_format:
73947371
case Intrinsic::amdgcn_struct_ptr_buffer_store_format:
7395-
return legalizeBufferStore(MI, Helper, false, true);
7372+
return legalizeBufferStore(MI, MRI, B, false, true);
73967373
case Intrinsic::amdgcn_raw_tbuffer_store:
73977374
case Intrinsic::amdgcn_raw_ptr_tbuffer_store:
73987375
case Intrinsic::amdgcn_struct_tbuffer_store:
73997376
case Intrinsic::amdgcn_struct_ptr_tbuffer_store:
7400-
return legalizeBufferStore(MI, Helper, true, true);
7377+
return legalizeBufferStore(MI, MRI, B, true, true);
74017378
case Intrinsic::amdgcn_raw_buffer_load:
74027379
case Intrinsic::amdgcn_raw_ptr_buffer_load:
74037380
case Intrinsic::amdgcn_raw_atomic_buffer_load:
@@ -7406,17 +7383,17 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
74067383
case Intrinsic::amdgcn_struct_ptr_buffer_load:
74077384
case Intrinsic::amdgcn_struct_atomic_buffer_load:
74087385
case Intrinsic::amdgcn_struct_ptr_atomic_buffer_load:
7409-
return legalizeBufferLoad(MI, Helper, false, false);
7386+
return legalizeBufferLoad(MI, MRI, B, false, false);
74107387
case Intrinsic::amdgcn_raw_buffer_load_format:
74117388
case Intrinsic::amdgcn_raw_ptr_buffer_load_format:
74127389
case Intrinsic::amdgcn_struct_buffer_load_format:
74137390
case Intrinsic::amdgcn_struct_ptr_buffer_load_format:
7414-
return legalizeBufferLoad(MI, Helper, true, false);
7391+
return legalizeBufferLoad(MI, MRI, B, true, false);
74157392
case Intrinsic::amdgcn_raw_tbuffer_load:
74167393
case Intrinsic::amdgcn_raw_ptr_tbuffer_load:
74177394
case Intrinsic::amdgcn_struct_tbuffer_load:
74187395
case Intrinsic::amdgcn_struct_ptr_tbuffer_load:
7419-
return legalizeBufferLoad(MI, Helper, true, true);
7396+
return legalizeBufferLoad(MI, MRI, B, true, true);
74207397
case Intrinsic::amdgcn_raw_buffer_atomic_swap:
74217398
case Intrinsic::amdgcn_raw_ptr_buffer_atomic_swap:
74227399
case Intrinsic::amdgcn_struct_buffer_atomic_swap:

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h

+7-5
Original file line numberDiff line numberDiff line change
@@ -195,13 +195,15 @@ class AMDGPULegalizerInfo final : public LegalizerInfo {
195195

196196
Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
197197
Register Reg, bool ImageStore = false) const;
198-
Register fixStoreSourceType(MachineIRBuilder &B, Register VData, LLT MemTy,
198+
Register fixStoreSourceType(MachineIRBuilder &B, Register VData,
199199
bool IsFormat) const;
200200

201-
bool legalizeBufferStore(MachineInstr &MI, LegalizerHelper &Helper,
202-
bool IsTyped, bool IsFormat) const;
203-
bool legalizeBufferLoad(MachineInstr &MI, LegalizerHelper &Helper,
204-
bool IsFormat, bool IsTyped) const;
201+
bool legalizeBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI,
202+
MachineIRBuilder &B, bool IsTyped,
203+
bool IsFormat) const;
204+
bool legalizeBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
205+
MachineIRBuilder &B, bool IsFormat,
206+
bool IsTyped) const;
205207
bool legalizeBufferAtomic(MachineInstr &MI, MachineIRBuilder &B,
206208
Intrinsic::ID IID) const;
207209

‎llvm/lib/Target/AMDGPU/SIRegisterInfo.td

+1-1
Original file line numberDiff line numberDiff line change
@@ -590,7 +590,7 @@ class RegisterTypes<list<ValueType> reg_types> {
590590

591591
def Reg16Types : RegisterTypes<[i16, f16, bf16]>;
592592
def Reg32Types : RegisterTypes<[i32, f32, v2i16, v2f16, v2bf16, p2, p3, p5, p6]>;
593-
def Reg64Types : RegisterTypes<[i64, f64, v2i32, v2f32, p0, p1, p4, v4i16, v4f16, v4bf16]>;
593+
def Reg64Types : RegisterTypes<[i64, f64, v2i32, v2f32, p0, v4i16, v4f16, v4bf16]>;
594594
def Reg96Types : RegisterTypes<[v3i32, v3f32]>;
595595
def Reg128Types : RegisterTypes<[v4i32, v4f32, v2i64, v2f64, v8i16, v8f16, v8bf16]>;
596596

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