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[AMDGPU] Enable asan LDS instrumentation
1 parent ebbbc73 commit 65dd67a

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-127
lines changed

‎llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp

Lines changed: 343 additions & 44 deletions
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‎llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-dynamic-lds-indirect-access.ll

Lines changed: 529 additions & 0 deletions
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‎llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-dynamic-lds-test.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals all --version 5
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; RUN: opt < %s -passes=asan -S -mtriple=amdgcn-- | FileCheck %s
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%llvm.amdgcn.sw.lds.k0.md.type = type { %llvm.amdgcn.sw.lds.k0.md.item, %llvm.amdgcn.sw.lds.k0.md.item }
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%llvm.amdgcn.sw.lds.k0.md.item = type { i32, i32, i32 }
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@llvm.amdgcn.sw.lds.k0 = internal addrspace(3) global ptr poison, no_sanitize_address, align 1, !absolute_symbol !0
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@llvm.amdgcn.k0.dynlds = external addrspace(3) global [0 x i8], no_sanitize_address, align 1, !absolute_symbol !1
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@llvm.amdgcn.sw.lds.k0.md = internal addrspace(1) global %llvm.amdgcn.sw.lds.k0.md.type { %llvm.amdgcn.sw.lds.k0.md.item { i32 0, i32 8, i32 8 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 8, i32 0, i32 0 } }, no_sanitize_address
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; Function Attrs: sanitize_address
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;.
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; CHECK: @llvm.amdgcn.sw.lds.k0 = internal addrspace(3) global ptr poison, no_sanitize_address, align 1, !absolute_symbol [[META0:![0-9]+]]
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; CHECK: @llvm.amdgcn.k0.dynlds = external addrspace(3) global [0 x i8], no_sanitize_address, align 1, !absolute_symbol [[META1:![0-9]+]]
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; CHECK: @llvm.amdgcn.sw.lds.k0.md = internal addrspace(1) global %0 { %1 { i32 0, i32 8, i32 32, i32 8, i32 24 }, %1 { i32 32, i32 0, i32 0, i32 0, i32 0 } }, no_sanitize_address, align 1
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; CHECK: @llvm.used = appending addrspace(1) global [1 x ptr] [ptr @asan.module_ctor], section "llvm.metadata"
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; CHECK: @___asan_globals_registered = common hidden addrspace(1) global i64 0
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; CHECK: @__start_asan_globals = extern_weak hidden addrspace(1) global i64
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; CHECK: @__stop_asan_globals = extern_weak hidden addrspace(1) global i64
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; CHECK: @llvm.global_ctors = appending addrspace(1) global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 1, ptr @asan.module_ctor, ptr @asan.module_ctor }]
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;.
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define amdgpu_kernel void @k0() #0 {
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; CHECK-LABEL: define amdgpu_kernel void @k0(
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; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[WID:.*]]:
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; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
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; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()
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; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z()
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; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP0]], [[TMP1]]
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; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP3]], [[TMP2]]
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; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
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; CHECK-NEXT: br i1 [[TMP5]], label %[[MALLOC:.*]], label %[[BB43:.*]]
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; CHECK: [[MALLOC]]:
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; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, align 4
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; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 0, i32 2), align 4
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; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP6]], [[TMP7]]
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; CHECK-NEXT: [[TMP9:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) [[TMP9]], i64 15
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; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 4
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; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr addrspace(4) [[TMP10]] to i64
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; CHECK-NEXT: [[TMP12:%.*]] = lshr i64 [[TMP11]], 3
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; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[TMP12]], 2147450880
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; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr
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; CHECK-NEXT: [[TMP15:%.*]] = load i8, ptr [[TMP14]], align 1
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; CHECK-NEXT: [[TMP16:%.*]] = icmp ne i8 [[TMP15]], 0
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; CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP11]], 7
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; CHECK-NEXT: [[TMP18:%.*]] = add i64 [[TMP17]], 3
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; CHECK-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP18]] to i8
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; CHECK-NEXT: [[TMP20:%.*]] = icmp sge i8 [[TMP19]], [[TMP15]]
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; CHECK-NEXT: [[TMP21:%.*]] = and i1 [[TMP16]], [[TMP20]]
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; CHECK-NEXT: [[TMP22:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP21]])
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; CHECK-NEXT: [[TMP23:%.*]] = icmp ne i64 [[TMP22]], 0
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; CHECK-NEXT: br i1 [[TMP23]], label %[[ASAN_REPORT:.*]], label %[[BB26:.*]], !prof [[PROF2:![0-9]+]]
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; CHECK: [[ASAN_REPORT]]:
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; CHECK-NEXT: br i1 [[TMP21]], label %[[BB24:.*]], label %[[BB25:.*]]
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; CHECK: [[BB24]]:
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; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP11]]) #[[ATTR7:[0-9]+]]
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; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
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; CHECK-NEXT: br label %[[BB25]]
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; CHECK: [[BB25]]:
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; CHECK-NEXT: br label %[[BB26]]
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; CHECK: [[BB26]]:
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; CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr addrspace(4) [[TMP10]], align 4
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; CHECK-NEXT: store i32 [[TMP27]], ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 1), align 4
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; CHECK-NEXT: [[TMP28:%.*]] = add i32 [[TMP27]], 0
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; CHECK-NEXT: [[TMP29:%.*]] = udiv i32 [[TMP28]], 1
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; CHECK-NEXT: [[TMP30:%.*]] = mul i32 [[TMP29]], 1
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; CHECK-NEXT: store i32 [[TMP30]], ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 2), align 4
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; CHECK-NEXT: [[TMP31:%.*]] = add i32 [[TMP8]], [[TMP30]]
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; CHECK-NEXT: [[TMP32:%.*]] = zext i32 [[TMP31]] to i64
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; CHECK-NEXT: [[TMP33:%.*]] = call ptr @llvm.returnaddress(i32 0)
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; CHECK-NEXT: [[TMP34:%.*]] = ptrtoint ptr [[TMP33]] to i64
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; CHECK-NEXT: [[TMP35:%.*]] = call i64 @__asan_malloc_impl(i64 [[TMP32]], i64 [[TMP34]])
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; CHECK-NEXT: [[TMP36:%.*]] = inttoptr i64 [[TMP35]] to ptr addrspace(1)
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; CHECK-NEXT: store ptr addrspace(1) [[TMP36]], ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
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; CHECK-NEXT: [[TMP37:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 0, i32 3), align 4
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; CHECK-NEXT: [[TMP38:%.*]] = zext i32 [[TMP37]] to i64
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; CHECK-NEXT: [[TMP39:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP36]], i64 [[TMP38]]
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; CHECK-NEXT: [[TMP40:%.*]] = ptrtoint ptr addrspace(1) [[TMP39]] to i64
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; CHECK-NEXT: [[TMP41:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 0, i32 4), align 4
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; CHECK-NEXT: [[TMP42:%.*]] = zext i32 [[TMP41]] to i64
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; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP40]], i64 [[TMP42]])
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; CHECK-NEXT: br label %[[BB43]]
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; CHECK: [[BB43]]:
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; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, %[[WID]] ], [ true, %[[BB26]] ]
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; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
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; CHECK-NEXT: [[TMP44:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 4
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; CHECK-NEXT: [[TMP45:%.*]] = getelementptr inbounds i8, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP44]]
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; CHECK-NEXT: call void @llvm.donothing() [ "ExplicitUse"(ptr addrspace(3) @llvm.amdgcn.k0.dynlds) ]
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; CHECK-NEXT: [[TMP46:%.*]] = ptrtoint ptr addrspace(3) [[TMP45]] to i32
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; CHECK-NEXT: [[TMP47:%.*]] = load ptr addrspace(1), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
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; CHECK-NEXT: [[TMP48:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP47]], i32 [[TMP46]]
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; CHECK-NEXT: [[TMP49:%.*]] = ptrtoint ptr addrspace(1) [[TMP48]] to i64
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; CHECK-NEXT: [[TMP50:%.*]] = lshr i64 [[TMP49]], 3
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; CHECK-NEXT: [[TMP51:%.*]] = add i64 [[TMP50]], 2147450880
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; CHECK-NEXT: [[TMP52:%.*]] = inttoptr i64 [[TMP51]] to ptr
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; CHECK-NEXT: [[TMP53:%.*]] = load i8, ptr [[TMP52]], align 1
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; CHECK-NEXT: [[TMP54:%.*]] = icmp ne i8 [[TMP53]], 0
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; CHECK-NEXT: [[TMP55:%.*]] = and i64 [[TMP49]], 7
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; CHECK-NEXT: [[TMP56:%.*]] = trunc i64 [[TMP55]] to i8
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; CHECK-NEXT: [[TMP57:%.*]] = icmp sge i8 [[TMP56]], [[TMP53]]
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; CHECK-NEXT: [[TMP58:%.*]] = and i1 [[TMP54]], [[TMP57]]
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; CHECK-NEXT: [[TMP59:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP58]])
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; CHECK-NEXT: [[TMP60:%.*]] = icmp ne i64 [[TMP59]], 0
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; CHECK-NEXT: br i1 [[TMP60]], label %[[ASAN_REPORT1:.*]], label %[[BB63:.*]], !prof [[PROF2]]
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; CHECK: [[ASAN_REPORT1]]:
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; CHECK-NEXT: br i1 [[TMP58]], label %[[BB61:.*]], label %[[BB62:.*]]
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; CHECK: [[BB61]]:
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; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP49]]) #[[ATTR7]]
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; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
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; CHECK-NEXT: br label %[[BB62]]
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; CHECK: [[BB62]]:
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; CHECK-NEXT: br label %[[BB63]]
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; CHECK: [[BB63]]:
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; CHECK-NEXT: store i8 7, ptr addrspace(3) [[TMP45]], align 4
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; CHECK-NEXT: br label %[[CONDFREE:.*]]
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; CHECK: [[CONDFREE]]:
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; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
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; CHECK-NEXT: br i1 [[XYZCOND]], label %[[FREE:.*]], label %[[END:.*]]
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; CHECK: [[FREE]]:
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; CHECK-NEXT: [[TMP64:%.*]] = load ptr addrspace(1), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
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; CHECK-NEXT: [[TMP65:%.*]] = call ptr @llvm.returnaddress(i32 0)
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; CHECK-NEXT: [[TMP66:%.*]] = ptrtoint ptr [[TMP65]] to i64
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; CHECK-NEXT: [[TMP67:%.*]] = ptrtoint ptr addrspace(1) [[TMP64]] to i64
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; CHECK-NEXT: call void @__asan_free_impl(i64 [[TMP67]], i64 [[TMP66]])
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; CHECK-NEXT: br label %[[END]]
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; CHECK: [[END]]:
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; CHECK-NEXT: ret void
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;
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WId:
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%0 = call i32 @llvm.amdgcn.workitem.id.x()
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%1 = call i32 @llvm.amdgcn.workitem.id.y()
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%2 = call i32 @llvm.amdgcn.workitem.id.z()
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%3 = or i32 %0, %1
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%4 = or i32 %3, %2
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%5 = icmp eq i32 %4, 0
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br i1 %5, label %Malloc, label %21
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Malloc: ; preds = %WId
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%6 = load i32, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, align 4
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%7 = load i32, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 0, i32 2), align 4
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%8 = add i32 %6, %7
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%9 = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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%10 = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) %9, i64 15
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store i32 %8, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 4
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%11 = load i32, ptr addrspace(4) %10, align 4
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store i32 %11, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 1), align 4
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%12 = add i32 %11, 0
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%13 = udiv i32 %12, 1
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%14 = mul i32 %13, 1
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store i32 %14, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 2), align 4
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%15 = add i32 %8, %14
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%16 = zext i32 %15 to i64
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%17 = call ptr @llvm.returnaddress(i32 0)
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%18 = ptrtoint ptr %17 to i64
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%19 = call i64 @__asan_malloc_impl(i64 %16, i64 %18)
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%20 = inttoptr i64 %19 to ptr addrspace(1)
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store ptr addrspace(1) %20, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
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br label %21
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21: ; preds = %Malloc, %WId
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%xyzCond = phi i1 [ false, %WId ], [ true, %Malloc ]
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call void @llvm.amdgcn.s.barrier()
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%22 = load i32, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 4
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%23 = getelementptr inbounds i8, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 %22
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call void @llvm.donothing() [ "ExplicitUse"(ptr addrspace(3) @llvm.amdgcn.k0.dynlds) ]
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store i8 7, ptr addrspace(3) %23, align 4
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br label %CondFree
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CondFree: ; preds = %21
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call void @llvm.amdgcn.s.barrier()
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br i1 %xyzCond, label %Free, label %End
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Free: ; preds = %CondFree
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%24 = load ptr addrspace(1), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
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%25 = call ptr @llvm.returnaddress(i32 0)
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%26 = ptrtoint ptr %25 to i64
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%27 = ptrtoint ptr addrspace(1) %24 to i64
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call void @__asan_free_impl(i64 %27, i64 %26)
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br label %End
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End: ; preds = %Free, %CondFree
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ret void
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}
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; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
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declare void @llvm.donothing() #1
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; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
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declare i32 @llvm.amdgcn.workitem.id.x() #2
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; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
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declare i32 @llvm.amdgcn.workitem.id.y() #2
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; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
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declare i32 @llvm.amdgcn.workitem.id.z() #2
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; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
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declare align 4 ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() #2
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; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
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declare ptr @llvm.returnaddress(i32 immarg) #1
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declare i64 @__asan_malloc_impl(i64, i64)
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; Function Attrs: convergent nocallback nofree nounwind willreturn
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declare void @llvm.amdgcn.s.barrier() #3
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declare void @__asan_free_impl(i64, i64)
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attributes #0 = { sanitize_address "amdgpu-lds-size"="8,8" }
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attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
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attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
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attributes #3 = { convergent nocallback nofree nounwind willreturn }
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!0 = !{i32 0, i32 1}
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!1 = !{i32 8, i32 9}
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;.
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; CHECK: attributes #[[ATTR0]] = { sanitize_address "amdgpu-lds-size"="32,32" }
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; CHECK: attributes #[[ATTR1:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(none) }
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; CHECK: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
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; CHECK: attributes #[[ATTR3:[0-9]+]] = { convergent nocallback nofree nounwind willreturn }
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; CHECK: attributes #[[ATTR4:[0-9]+]] = { convergent nocallback nofree nounwind willreturn memory(none) }
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; CHECK: attributes #[[ATTR5:[0-9]+]] = { convergent nocallback nofree nounwind }
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; CHECK: attributes #[[ATTR6:[0-9]+]] = { nounwind }
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; CHECK: attributes #[[ATTR7]] = { nomerge }
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;.
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; CHECK: [[META0]] = !{i32 0, i32 1}
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; CHECK: [[META1]] = !{i32 32, i32 33}
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; CHECK: [[PROF2]] = !{!"branch_weights", i32 1, i32 1048575}
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;.

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