fixup! [RISCV] Handle zeroinitializer of vector tuple Type

Author: 4vtomat

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

@@ -6434,9 +6434,6 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
       return getNode(ISD::VECREDUCE_AND, DL, VT, N1);
     break;
   case ISD::SPLAT_VECTOR:
-    // RISC-V vector tuple type is not a vector type.
-    if (VT.isRISCVVectorTuple())
-      break;
     assert(VT.isVector() && "Wrong return type!");
     // FIXME: Hexagon uses i32 scalar for a floating point zero vector so allow
     // that for now.

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

@@ -1899,8 +1899,12 @@ SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
     if (VT.isRISCVVectorTuple()) {
       assert(C->isNullValue() && "Can only zero this target type!");
       return NodeMap[V] = DAG.getNode(
-                 ISD::SPLAT_VECTOR, getCurSDLoc(), VT,
-                 DAG.getConstant(0, getCurSDLoc(), MVT::getIntegerVT(8)));
+                 ISD::BITCAST, getCurSDLoc(), VT,
+                 DAG.getNode(
+                     ISD::SPLAT_VECTOR, getCurSDLoc(),
+                     MVT::getScalableVectorVT(
+                         MVT::i8, VT.getSizeInBits().getKnownMinValue() / 8),
+                     DAG.getConstant(0, getCurSDLoc(), MVT::getIntegerVT(8))));
     }
 
     VectorType *VecTy = cast<VectorType>(V->getType());

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

@@ -57,18 +57,14 @@ void RISCVDAGToDAGISel::PreprocessISelDAG() {
 
     SDValue Result;
     switch (N->getOpcode()) {
-    case ISD::SPLAT_VECTOR: {
-      // Convert integer SPLAT_VECTOR to VMV_V_X_VL and floating-point
-      // SPLAT_VECTOR to VFMV_V_F_VL to reduce isel burden.
+    case ISD::BITCAST: {
       MVT VT = N->getSimpleValueType(0);
-      unsigned Opc =
-          VT.isInteger() ? RISCVISD::VMV_V_X_VL : RISCVISD::VFMV_V_F_VL;
       SDLoc DL(N);
       SDValue VL = CurDAG->getRegister(RISCV::X0, Subtarget->getXLenVT());
-
-      if (VT.isRISCVVectorTuple()) {
+      if (VT.isRISCVVectorTuple() &&
+          N->getOperand(0)->getOpcode() == ISD::SPLAT_VECTOR) {
         unsigned NF = VT.getRISCVVectorTupleNumFields();
-        unsigned NumScalElts = VT.getSizeInBits() / (NF * 8);
+        unsigned NumScalElts = VT.getSizeInBits().getKnownMinValue() / (NF * 8);
         SDValue EltVal = CurDAG->getConstant(0, DL, Subtarget->getXLenVT());
         MVT ScalTy =
             MVT::getScalableVectorVT(MVT::getIntegerVT(8), NumScalElts);
@@ -80,10 +76,17 @@ void RISCVDAGToDAGISel::PreprocessISelDAG() {
         for (unsigned i = 0; i < NF; ++i)
           Result = CurDAG->getNode(RISCVISD::TUPLE_INSERT, DL, VT, Result,
                                    Splat, CurDAG->getVectorIdxConstant(i, DL));
-
-        break;
       }
-
+      break;
+    }
+    case ISD::SPLAT_VECTOR: {
+      // Convert integer SPLAT_VECTOR to VMV_V_X_VL and floating-point
+      // SPLAT_VECTOR to VFMV_V_F_VL to reduce isel burden.
+      MVT VT = N->getSimpleValueType(0);
+      unsigned Opc =
+          VT.isInteger() ? RISCVISD::VMV_V_X_VL : RISCVISD::VFMV_V_F_VL;
+      SDLoc DL(N);
+      SDValue VL = CurDAG->getRegister(RISCV::X0, Subtarget->getXLenVT());
       SDValue Src = N->getOperand(0);
       if (VT.isInteger())
         Src = CurDAG->getNode(ISD::ANY_EXTEND, DL, Subtarget->getXLenVT(),