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KoolJBlackKoolJBlack
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unsigned emulation for i4
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‎mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp

Lines changed: 78 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -880,6 +880,38 @@ static Value rewriteI4ToI8SignedExt(PatternRewriter &rewriter, Location loc,
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return rewriter.create<vector::InterleaveOp>(loc, low, high);
881881
}
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/// Rewrite the i4 -> i8 unsigned extension into a sequence of shuffles and
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/// bitwise ops that take advantage of high-level information to avoid leaving
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/// LLVM to scramble with peephole optimizations.
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static Value rewriteI4ToI8UnsignedExt(PatternRewriter &rewriter, Location loc,
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Value srcValue) {
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VectorType srcVecType = cast<VectorType>(srcValue.getType());
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assert(srcVecType.getElementType().isSignlessInteger(4) &&
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"Expected i4 type");
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// 1. Generate a bitcast vector<Xxi4> -> vector<X/2xi8>.
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SmallVector<int64_t> i8VecShape = llvm::to_vector(srcVecType.getShape());
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constexpr int64_t i4Toi8BitwidthFactor = 2;
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i8VecShape.back() = i8VecShape.back() / i4Toi8BitwidthFactor;
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auto i8VecType = VectorType::get(i8VecShape, rewriter.getI8Type());
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Value i8Vector = rewriter.create<vector::BitCastOp>(loc, i8VecType, srcValue);
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// 2 Extend the i4 elements using shifts & masking. Low i4 elemens of each
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// byte are place in one vector and the high i4 elements in another vector.
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constexpr unsigned char lowBitsMask = 15; // Equivalent to [0000IIII] bit mask
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auto lowBitsMaskValues = rewriter.create<arith::ConstantOp>(
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loc, DenseElementsAttr::get(i8VecType, lowBitsMask));
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Value low = rewriter.create<arith::AndIOp>(loc, i8Vector.getType(), i8Vector,
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lowBitsMaskValues);
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constexpr int8_t highBitsToShift = 4;
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auto highShiftValues = rewriter.create<arith::ConstantOp>(
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loc, DenseElementsAttr::get(i8VecType, highBitsToShift));
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Value high = rewriter.create<arith::ShRSIOp>(loc, i8Vector, highShiftValues);
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// 3. Interleave low and high i8 elements.
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return rewriter.create<vector::InterleaveOp>(loc, low, high);
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}
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/// Rewrite the i8 -> i4 truncation into a sequence of shuffles and bitwise ops
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/// that take advantage of high-level information to avoid leaving LLVM to
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/// scramble with peephole optimizations.
@@ -1099,6 +1131,50 @@ struct RewriteAlignedSubByteIntSignedExt : OpRewritePattern<ConversionOpType> {
10991131
}
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};
11011133

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/// Rewrite the i4 -> i8 part of any unsigned conversion into a sequence of
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/// shuffles and bitwise ops that take advantage of high-level information to
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/// avoid leaving LLVM to scramble with peephole optimizations.
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///
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/// For example:
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/// arith.extui %in : vector<8xi4> to vector<8xi32>
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/// is rewritten as
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/// %0 = vector.bitcast %in : vector<8xi4> to vector<4xi8>
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/// %1 = arith.andi %0, 15 : vector<4xi8>
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/// %2 = arith.shrsi %0, 4 : vector<4xi8>
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/// %3 = vector.interleave %1, %2 : vector<4xi8>
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/// %4 = arith.extsi %3 : vector<8xi8> to vector<8xi32>
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///
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template <typename ConversionOpType>
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struct RewriteAlignedSubByteIntUnsignedExt
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: OpRewritePattern<ConversionOpType> {
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using OpRewritePattern<ConversionOpType>::OpRewritePattern;
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LogicalResult matchAndRewrite(ConversionOpType conversionOp,
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PatternRewriter &rewriter) const override {
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// Verify the preconditions.
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Value srcValue = conversionOp.getIn();
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auto srcVecType = dyn_cast<VectorType>(srcValue.getType());
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auto dstVecType = dyn_cast<VectorType>(conversionOp.getType());
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if (failed(
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commonConversionPrecondition(rewriter, dstVecType, conversionOp)))
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return failure();
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// Check general alignment preconditions.
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if (failed(alignedConversionPrecondition(rewriter, srcVecType, dstVecType,
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conversionOp)))
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return failure();
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// Perform the rewrite.
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Value subByteExt =
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rewriteI4ToI8UnsignedExt(rewriter, conversionOp.getLoc(), srcValue);
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// Finalize the rewrite.
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rewriter.replaceOpWithNewOp<ConversionOpType>(
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conversionOp, conversionOp.getType(), subByteExt);
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return success();
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}
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};
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/// Rewrite the i8 -> i4 part of any truncation into a sequence of shuffles and
11031179
/// bitwise ops that take advantage of high-level information to avoid leaving
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/// LLVM to scramble with peephole optimizations.
@@ -1233,6 +1309,8 @@ void vector::populateVectorNarrowTypeRewritePatterns(
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RewriteAlignedSubByteIntSignedExt<arith::SIToFPOp>,
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RewriteAlignedSubByteIntTrunc>(patterns.getContext(),
12351311
benefit.getBenefit() + 1);
1312+
patterns.add<RewriteAlignedSubByteIntUnsignedExt<arith::ExtUIOp>>(
1313+
patterns.getContext(), benefit.getBenefit() + 1);
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}
12371315

12381316
void vector::populateVectorTransposeNarrowTypeRewritePatterns(

‎mlir/test/Dialect/Vector/vector-rewrite-narrow-types.mlir

Lines changed: 44 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -324,6 +324,50 @@ func.func @i7_transpose(%a: vector<8x16xi7>) -> vector<16x8xi7> {
324324
return %0 : vector<16x8xi7>
325325
}
326326

327+
// CHECK-LABEL: func.func @aligned_extui(
328+
func.func @aligned_extui(%a: vector<8xi4>) -> vector<8xi32> {
329+
// CHECK-SAME: %[[VAL_0:.*]]: vector<8xi4>) -> vector<8xi32> {
330+
// CHECK: %[[VAL_1:.*]] = arith.constant dense<4> : vector<4xi8>
331+
// CHECK: %[[VAL_2:.*]] = arith.constant dense<15> : vector<4xi8>
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// CHECK: %[[VAL_3:.*]] = vector.bitcast %[[VAL_0]] : vector<8xi4> to vector<4xi8>
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// CHECK: %[[VAL_4:.*]] = arith.andi %[[VAL_3]], %[[VAL_2]] : vector<4xi8>
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// CHECK: %[[VAL_5:.*]] = arith.shrsi %[[VAL_3]], %[[VAL_1]] : vector<4xi8>
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// CHECK: %[[VAL_6:.*]] = vector.interleave %[[VAL_4]], %[[VAL_5]] : vector<4xi8>
336+
// CHECK: %[[VAL_7:.*]] = arith.extui %[[VAL_6]] : vector<8xi8> to vector<8xi32>
337+
%0 = arith.extui %a : vector<8xi4> to vector<8xi32>
338+
return %0 : vector<8xi32>
339+
}
340+
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// CHECK-LABEL: func.func @aligned_extui_2d(
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func.func @aligned_extui_2d(%a: vector<8x32xi4>) -> vector<8x32xi32> {
344+
// CHECK-SAME: %[[VAL_0:.*]]: vector<8x32xi4>) -> vector<8x32xi32> {
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// CHECK: %[[VAL_1:.*]] = arith.constant dense<4> : vector<8x16xi8>
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// CHECK: %[[VAL_2:.*]] = arith.constant dense<15> : vector<8x16xi8>
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// CHECK: %[[VAL_3:.*]] = vector.bitcast %[[VAL_0]] : vector<8x32xi4> to vector<8x16xi8>
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// CHECK: %[[VAL_4:.*]] = arith.andi %[[VAL_3]], %[[VAL_2]] : vector<8x16xi8>
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// CHECK: %[[VAL_5:.*]] = arith.shrsi %[[VAL_3]], %[[VAL_1]] : vector<8x16xi8>
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// CHECK: %[[VAL_6:.*]] = vector.interleave %[[VAL_4]], %[[VAL_5]] : vector<8x16xi8>
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// CHECK: %[[VAL_7:.*]] = arith.extui %[[VAL_6]] : vector<8x32xi8> to vector<8x32xi32>
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// CHECK: return %[[VAL_7]] : vector<8x32xi32>
353+
%0 = arith.extui %a : vector<8x32xi4> to vector<8x32xi32>
354+
return %0 : vector<8x32xi32>
355+
}
356+
357+
358+
// CHECK-LABEL: func.func @aligned_extui_base_case(
359+
func.func @aligned_extui_base_case(%a: vector<8xi4>) -> vector<8xi8> {
360+
// CHECK-SAME: %[[VAL_0:.*]]: vector<8xi4>) -> vector<8xi8> {
361+
// CHECK: %[[VAL_1:.*]] = arith.constant dense<4> : vector<4xi8>
362+
// CHECK: %[[VAL_2:.*]] = arith.constant dense<15> : vector<4xi8>
363+
// CHECK: %[[VAL_3:.*]] = vector.bitcast %[[VAL_0]] : vector<8xi4> to vector<4xi8>
364+
// CHECK: %[[VAL_4:.*]] = arith.andi %[[VAL_3]], %[[VAL_2]] : vector<4xi8>
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// CHECK: %[[VAL_5:.*]] = arith.shrsi %[[VAL_3]], %[[VAL_1]] : vector<4xi8>
366+
// CHECK: %[[VAL_6:.*]] = vector.interleave %[[VAL_4]], %[[VAL_5]] : vector<4xi8>
367+
%0 = arith.extui %a : vector<8xi4> to vector<8xi8>
368+
return %0 : vector<8xi8>
369+
}
370+
327371
module attributes {transform.with_named_sequence} {
328372
transform.named_sequence @__transform_main(%module_op: !transform.any_op {transform.readonly}) {
329373
%f = transform.structured.match ops{["func.func"]} in %module_op
@@ -335,4 +379,3 @@ module attributes {transform.with_named_sequence} {
335379
transform.yield
336380
}
337381
}
338-

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