[RISCV][GISel] Make s64 G_LOAD/G_STORE legal on RV32 with D extension.

topperc · topperc · commit 6930c3a49baf · 2023-10-31T23:40:13.000-07:00
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -111,6 +111,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
                                                {s64, p0, s64, 64}});
     ExtLoadActions.legalForTypesWithMemDesc(
         {{s64, p0, s8, 8}, {s64, p0, s16, 16}, {s64, p0, s32, 32}});
+  } else if (ST.hasStdExtD()) {
+    LoadStoreActions.legalForTypesWithMemDesc({{s64, p0, s64, 64}});
   }
   LoadStoreActions.clampScalar(0, s32, sXLen).lower();
   ExtLoadActions.widenScalarToNextPow2(0).clampScalar(0, s32, sXLen).lower();

Original file line number	Diff line number	Diff line change
`@@ -111,6 +111,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {`
`111`	`111`	`{s64, p0, s64, 64}});`
`112`	`112`	`ExtLoadActions.legalForTypesWithMemDesc(`
`113`	`113`	`{{s64, p0, s8, 8}, {s64, p0, s16, 16}, {s64, p0, s32, 32}});`
	`114`	`+ } else if (ST.hasStdExtD()) {`
	`115`	`+ LoadStoreActions.legalForTypesWithMemDesc({{s64, p0, s64, 64}});`
`114`	`116`	`}`
`115`	`117`	`LoadStoreActions.clampScalar(0, s32, sXLen).lower();`
`116`	`118`	`ExtLoadActions.widenScalarToNextPow2(0).clampScalar(0, s32, sXLen).lower();`