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[Xtensa] Implement Xtensa MAC16 Option. (#130004)
1 parent bfdeb58 commit 69527b0

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7 files changed

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-2
lines changed

7 files changed

+654
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llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp

Lines changed: 43 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -73,8 +73,50 @@ static DecodeStatus DecodeARRegisterClass(MCInst &Inst, uint64_t RegNo,
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return MCDisassembler::Success;
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}
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static const MCPhysReg MRDecoderTable[] = {Xtensa::M0, Xtensa::M1, Xtensa::M2,
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Xtensa::M3};
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static DecodeStatus DecodeMRRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo >= std::size(MRDecoderTable))
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return MCDisassembler::Fail;
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MCPhysReg Reg = MRDecoderTable[RegNo];
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static const MCPhysReg MR01DecoderTable[] = {Xtensa::M0, Xtensa::M1};
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static DecodeStatus DecodeMR01RegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 2)
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return MCDisassembler::Fail;
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MCPhysReg Reg = MR01DecoderTable[RegNo];
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static const MCPhysReg MR23DecoderTable[] = {Xtensa::M2, Xtensa::M3};
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static DecodeStatus DecodeMR23RegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo != 2 && RegNo != 3)
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return MCDisassembler::Fail;
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MCPhysReg Reg = MR23DecoderTable[RegNo - 2];
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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const MCPhysReg SRDecoderTable[] = {
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Xtensa::SAR, 3, Xtensa::WINDOWBASE, 72, Xtensa::WINDOWSTART, 73};
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Xtensa::SAR, 3, Xtensa::ACCLO, 16, Xtensa::ACCHI, 17,
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Xtensa::M0, 32, Xtensa::M1, 33, Xtensa::M2, 34,
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Xtensa::M3, 35, Xtensa::WINDOWBASE, 72, Xtensa::WINDOWSTART, 73};
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static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,

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