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[AArch64][GlobalISel] Pre-commit Test for Combine MUL(AND(LSHR)) to CMLT
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‎llvm/test/CodeGen/AArch64/mulcmle.ll

Lines changed: 107 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -1,78 +1,155 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s
2+
; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3+
; RUN: llc -mtriple=aarch64 %s -o - -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
34

45
define <1 x i64> @v1i64(<1 x i64> %a) {
5-
; CHECK-LABEL: v1i64:
6-
; CHECK: // %bb.0:
7-
; CHECK-NEXT: cmlt v0.2s, v0.2s, #0
8-
; CHECK-NEXT: ret
6+
; CHECK-SD-LABEL: v1i64:
7+
; CHECK-SD: // %bb.0:
8+
; CHECK-SD-NEXT: cmlt v0.2s, v0.2s, #0
9+
; CHECK-SD-NEXT: ret
10+
;
11+
; CHECK-GI-LABEL: v1i64:
12+
; CHECK-GI: // %bb.0:
13+
; CHECK-GI-NEXT: fmov x8, d0
14+
; CHECK-GI-NEXT: lsr x8, x8, #31
15+
; CHECK-GI-NEXT: and x8, x8, #0x100000001
16+
; CHECK-GI-NEXT: lsl x9, x8, #32
17+
; CHECK-GI-NEXT: sub x8, x9, x8
18+
; CHECK-GI-NEXT: fmov d0, x8
19+
; CHECK-GI-NEXT: ret
920
%b = lshr <1 x i64> %a, <i64 31>
1021
%c = and <1 x i64> %b, <i64 4294967297>
1122
%d = mul nuw <1 x i64> %c, <i64 4294967295>
1223
ret <1 x i64> %d
1324
}
1425

1526
define <2 x i64> @v2i64(<2 x i64> %a) {
16-
; CHECK-LABEL: v2i64:
17-
; CHECK: // %bb.0:
18-
; CHECK-NEXT: cmlt v0.4s, v0.4s, #0
19-
; CHECK-NEXT: ret
27+
; CHECK-SD-LABEL: v2i64:
28+
; CHECK-SD: // %bb.0:
29+
; CHECK-SD-NEXT: cmlt v0.4s, v0.4s, #0
30+
; CHECK-SD-NEXT: ret
31+
;
32+
; CHECK-GI-LABEL: v2i64:
33+
; CHECK-GI: // %bb.0:
34+
; CHECK-GI-NEXT: movi v1.4s, #1
35+
; CHECK-GI-NEXT: ushr v0.2d, v0.2d, #31
36+
; CHECK-GI-NEXT: movi v2.2d, #0x000000ffffffff
37+
; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
38+
; CHECK-GI-NEXT: mov d3, v2.d[1]
39+
; CHECK-GI-NEXT: fmov x9, d2
40+
; CHECK-GI-NEXT: mov d1, v0.d[1]
41+
; CHECK-GI-NEXT: fmov x8, d0
42+
; CHECK-GI-NEXT: fmov x10, d3
43+
; CHECK-GI-NEXT: mul x8, x8, x9
44+
; CHECK-GI-NEXT: fmov x9, d1
45+
; CHECK-GI-NEXT: mul x9, x9, x10
46+
; CHECK-GI-NEXT: fmov d0, x8
47+
; CHECK-GI-NEXT: mov v0.d[1], x9
48+
; CHECK-GI-NEXT: ret
2049
%b = lshr <2 x i64> %a, <i64 31, i64 31>
2150
%c = and <2 x i64> %b, <i64 4294967297, i64 4294967297>
2251
%d = mul nuw <2 x i64> %c, <i64 4294967295, i64 4294967295>
2352
ret <2 x i64> %d
2453
}
2554

2655
define <2 x i32> @v2i32(<2 x i32> %a) {
27-
; CHECK-LABEL: v2i32:
28-
; CHECK: // %bb.0:
29-
; CHECK-NEXT: cmlt v0.4h, v0.4h, #0
30-
; CHECK-NEXT: ret
56+
; CHECK-SD-LABEL: v2i32:
57+
; CHECK-SD: // %bb.0:
58+
; CHECK-SD-NEXT: cmlt v0.4h, v0.4h, #0
59+
; CHECK-SD-NEXT: ret
60+
;
61+
; CHECK-GI-LABEL: v2i32:
62+
; CHECK-GI: // %bb.0:
63+
; CHECK-GI-NEXT: movi v1.4h, #1
64+
; CHECK-GI-NEXT: ushr v0.2s, v0.2s, #15
65+
; CHECK-GI-NEXT: movi d2, #0x00ffff0000ffff
66+
; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
67+
; CHECK-GI-NEXT: mul v0.2s, v0.2s, v2.2s
68+
; CHECK-GI-NEXT: ret
3169
%b = lshr <2 x i32> %a, <i32 15, i32 15>
3270
%c = and <2 x i32> %b, <i32 65537, i32 65537>
3371
%d = mul nuw <2 x i32> %c, <i32 65535, i32 65535>
3472
ret <2 x i32> %d
3573
}
3674

3775
define <4 x i32> @v4i32(<4 x i32> %a) {
38-
; CHECK-LABEL: v4i32:
39-
; CHECK: // %bb.0:
40-
; CHECK-NEXT: cmlt v0.8h, v0.8h, #0
41-
; CHECK-NEXT: ret
76+
; CHECK-SD-LABEL: v4i32:
77+
; CHECK-SD: // %bb.0:
78+
; CHECK-SD-NEXT: cmlt v0.8h, v0.8h, #0
79+
; CHECK-SD-NEXT: ret
80+
;
81+
; CHECK-GI-LABEL: v4i32:
82+
; CHECK-GI: // %bb.0:
83+
; CHECK-GI-NEXT: movi v1.8h, #1
84+
; CHECK-GI-NEXT: ushr v0.4s, v0.4s, #15
85+
; CHECK-GI-NEXT: movi v2.2d, #0x00ffff0000ffff
86+
; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
87+
; CHECK-GI-NEXT: mul v0.4s, v0.4s, v2.4s
88+
; CHECK-GI-NEXT: ret
4289
%b = lshr <4 x i32> %a, <i32 15, i32 15, i32 15, i32 15>
4390
%c = and <4 x i32> %b, <i32 65537, i32 65537, i32 65537, i32 65537>
4491
%d = mul nuw <4 x i32> %c, <i32 65535, i32 65535, i32 65535, i32 65535>
4592
ret <4 x i32> %d
4693
}
4794

4895
define <8 x i32> @v8i32(<8 x i32> %a) {
49-
; CHECK-LABEL: v8i32:
50-
; CHECK: // %bb.0:
51-
; CHECK-NEXT: cmlt v0.8h, v0.8h, #0
52-
; CHECK-NEXT: cmlt v1.8h, v1.8h, #0
53-
; CHECK-NEXT: ret
96+
; CHECK-SD-LABEL: v8i32:
97+
; CHECK-SD: // %bb.0:
98+
; CHECK-SD-NEXT: cmlt v0.8h, v0.8h, #0
99+
; CHECK-SD-NEXT: cmlt v1.8h, v1.8h, #0
100+
; CHECK-SD-NEXT: ret
101+
;
102+
; CHECK-GI-LABEL: v8i32:
103+
; CHECK-GI: // %bb.0:
104+
; CHECK-GI-NEXT: movi v2.8h, #1
105+
; CHECK-GI-NEXT: ushr v0.4s, v0.4s, #15
106+
; CHECK-GI-NEXT: ushr v1.4s, v1.4s, #15
107+
; CHECK-GI-NEXT: movi v3.2d, #0x00ffff0000ffff
108+
; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b
109+
; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b
110+
; CHECK-GI-NEXT: mul v0.4s, v0.4s, v3.4s
111+
; CHECK-GI-NEXT: mul v1.4s, v1.4s, v3.4s
112+
; CHECK-GI-NEXT: ret
54113
%b = lshr <8 x i32> %a, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
55114
%c = and <8 x i32> %b, <i32 65537, i32 65537, i32 65537, i32 65537, i32 65537, i32 65537, i32 65537, i32 65537>
56115
%d = mul nuw <8 x i32> %c, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
57116
ret <8 x i32> %d
58117
}
59118

60119
define <4 x i16> @v4i16(<4 x i16> %a) {
61-
; CHECK-LABEL: v4i16:
62-
; CHECK: // %bb.0:
63-
; CHECK-NEXT: cmlt v0.8b, v0.8b, #0
64-
; CHECK-NEXT: ret
120+
; CHECK-SD-LABEL: v4i16:
121+
; CHECK-SD: // %bb.0:
122+
; CHECK-SD-NEXT: cmlt v0.8b, v0.8b, #0
123+
; CHECK-SD-NEXT: ret
124+
;
125+
; CHECK-GI-LABEL: v4i16:
126+
; CHECK-GI: // %bb.0:
127+
; CHECK-GI-NEXT: movi v1.8b, #1
128+
; CHECK-GI-NEXT: ushr v0.4h, v0.4h, #7
129+
; CHECK-GI-NEXT: movi d2, #0xff00ff00ff00ff
130+
; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
131+
; CHECK-GI-NEXT: mul v0.4h, v0.4h, v2.4h
132+
; CHECK-GI-NEXT: ret
65133
%b = lshr <4 x i16> %a, <i16 7, i16 7, i16 7, i16 7>
66134
%c = and <4 x i16> %b, <i16 257, i16 257, i16 257, i16 257>
67135
%d = mul nuw <4 x i16> %c, <i16 255, i16 255, i16 255, i16 255>
68136
ret <4 x i16> %d
69137
}
70138

71139
define <8 x i16> @v8i16(<8 x i16> %a) {
72-
; CHECK-LABEL: v8i16:
73-
; CHECK: // %bb.0:
74-
; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
75-
; CHECK-NEXT: ret
140+
; CHECK-SD-LABEL: v8i16:
141+
; CHECK-SD: // %bb.0:
142+
; CHECK-SD-NEXT: cmlt v0.16b, v0.16b, #0
143+
; CHECK-SD-NEXT: ret
144+
;
145+
; CHECK-GI-LABEL: v8i16:
146+
; CHECK-GI: // %bb.0:
147+
; CHECK-GI-NEXT: movi v1.16b, #1
148+
; CHECK-GI-NEXT: ushr v0.8h, v0.8h, #7
149+
; CHECK-GI-NEXT: movi v2.2d, #0xff00ff00ff00ff
150+
; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
151+
; CHECK-GI-NEXT: mul v0.8h, v0.8h, v2.8h
152+
; CHECK-GI-NEXT: ret
76153
%b = lshr <8 x i16> %a, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
77154
%c = and <8 x i16> %b, <i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257>
78155
%d = mul nuw <8 x i16> %c, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>

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