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[RISCV][GISel] Promote s32 G_CONSTANT on RV64.
1 parent 0c5bf56 commit 6a857fe

31 files changed

+1255
-1881
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

+3-2
Original file line numberDiff line numberDiff line change
@@ -230,10 +230,11 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
230230
}
231231

232232
getActionDefinitionsBuilder(G_CONSTANT)
233-
.legalFor({s32, p0})
233+
.legalFor({p0})
234+
.legalFor(!ST.is64Bit(), {s32})
234235
.customFor(ST.is64Bit(), {s64})
235236
.widenScalarToNextPow2(0)
236-
.clampScalar(0, s32, sXLen);
237+
.clampScalar(0, sXLen, sXLen);
237238

238239
// TODO: transform illegal vector types into legal vector type
239240
getActionDefinitionsBuilder(

‎llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll

+1-4
Original file line numberDiff line numberDiff line change
@@ -123,10 +123,7 @@ define i32 @subi_i32(i32 %a) {
123123
;
124124
; RV64IM-LABEL: subi_i32:
125125
; RV64IM: # %bb.0: # %entry
126-
; RV64IM-NEXT: li a1, 1
127-
; RV64IM-NEXT: slli a1, a1, 32
128-
; RV64IM-NEXT: addi a1, a1, -1234
129-
; RV64IM-NEXT: add a0, a0, a1
126+
; RV64IM-NEXT: addi a0, a0, -1234
130127
; RV64IM-NEXT: ret
131128
entry:
132129
%0 = sub i32 %a, 1234

‎llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll

+30-34
Original file line numberDiff line numberDiff line change
@@ -115,18 +115,17 @@ define i7 @bitreverse_i7(i7 %x) {
115115
; RV64-NEXT: slli a2, a0, 4
116116
; RV64-NEXT: andi a2, a2, 32
117117
; RV64-NEXT: or a1, a1, a2
118-
; RV64-NEXT: li a2, 2
119-
; RV64-NEXT: slli a3, a0, 2
120-
; RV64-NEXT: andi a3, a3, 16
118+
; RV64-NEXT: slli a2, a0, 2
119+
; RV64-NEXT: andi a2, a2, 16
121120
; RV64-NEXT: andi a0, a0, 127
122-
; RV64-NEXT: andi a4, a0, 8
123-
; RV64-NEXT: or a3, a3, a4
124-
; RV64-NEXT: or a1, a1, a3
125-
; RV64-NEXT: srli a3, a0, 2
126-
; RV64-NEXT: andi a3, a3, 4
127-
; RV64-NEXT: srli a4, a0, 4
128-
; RV64-NEXT: and a2, a4, a2
129-
; RV64-NEXT: or a2, a3, a2
121+
; RV64-NEXT: andi a3, a0, 8
122+
; RV64-NEXT: or a2, a2, a3
123+
; RV64-NEXT: or a1, a1, a2
124+
; RV64-NEXT: srli a2, a0, 2
125+
; RV64-NEXT: andi a2, a2, 4
126+
; RV64-NEXT: srli a3, a0, 4
127+
; RV64-NEXT: andi a3, a3, 2
128+
; RV64-NEXT: or a2, a2, a3
130129
; RV64-NEXT: or a1, a1, a2
131130
; RV64-NEXT: srli a0, a0, 6
132131
; RV64-NEXT: or a0, a1, a0
@@ -172,39 +171,36 @@ define i24 @bitreverse_i24(i24 %x) {
172171
;
173172
; RV64-LABEL: bitreverse_i24:
174173
; RV64: # %bb.0:
175-
; RV64-NEXT: lui a1, 4096
176-
; RV64-NEXT: addiw a1, a1, -1
177-
; RV64-NEXT: slli a2, a0, 16
178-
; RV64-NEXT: and a0, a0, a1
174+
; RV64-NEXT: slli a1, a0, 16
175+
; RV64-NEXT: lui a2, 4096
176+
; RV64-NEXT: addiw a2, a2, -1
177+
; RV64-NEXT: and a0, a0, a2
179178
; RV64-NEXT: srli a0, a0, 16
180-
; RV64-NEXT: or a0, a0, a2
181-
; RV64-NEXT: lui a2, 65521
182-
; RV64-NEXT: addiw a2, a2, -241
183-
; RV64-NEXT: slli a2, a2, 4
184-
; RV64-NEXT: and a3, a2, a1
179+
; RV64-NEXT: or a0, a0, a1
180+
; RV64-NEXT: lui a1, 1048335
181+
; RV64-NEXT: addiw a1, a1, 240
182+
; RV64-NEXT: and a3, a1, a2
185183
; RV64-NEXT: and a3, a0, a3
186184
; RV64-NEXT: srli a3, a3, 4
187185
; RV64-NEXT: slli a0, a0, 4
188-
; RV64-NEXT: and a0, a0, a2
186+
; RV64-NEXT: and a0, a0, a1
189187
; RV64-NEXT: or a0, a3, a0
190-
; RV64-NEXT: lui a2, 261939
191-
; RV64-NEXT: addiw a2, a2, 819
192-
; RV64-NEXT: slli a2, a2, 2
193-
; RV64-NEXT: and a3, a2, a1
188+
; RV64-NEXT: lui a1, 1047757
189+
; RV64-NEXT: addiw a1, a1, -820
190+
; RV64-NEXT: and a3, a1, a2
194191
; RV64-NEXT: and a3, a0, a3
195192
; RV64-NEXT: srli a3, a3, 2
196193
; RV64-NEXT: slli a0, a0, 2
197-
; RV64-NEXT: and a0, a0, a2
194+
; RV64-NEXT: and a0, a0, a1
198195
; RV64-NEXT: or a0, a3, a0
199-
; RV64-NEXT: lui a2, 523605
200-
; RV64-NEXT: addiw a2, a2, 1365
201-
; RV64-NEXT: slli a2, a2, 1
202-
; RV64-NEXT: and a1, a2, a1
203-
; RV64-NEXT: and a1, a0, a1
204-
; RV64-NEXT: srli a1, a1, 1
196+
; RV64-NEXT: lui a1, 1047211
197+
; RV64-NEXT: addiw a1, a1, -1366
198+
; RV64-NEXT: and a2, a1, a2
199+
; RV64-NEXT: and a2, a0, a2
200+
; RV64-NEXT: srli a2, a2, 1
205201
; RV64-NEXT: slli a0, a0, 1
206-
; RV64-NEXT: and a0, a0, a2
207-
; RV64-NEXT: or a0, a1, a0
202+
; RV64-NEXT: and a0, a0, a1
203+
; RV64-NEXT: or a0, a2, a0
208204
; RV64-NEXT: ret
209205
%rev = call i24 @llvm.bitreverse.i24(i24 %x)
210206
ret i24 %rev

‎llvm/test/CodeGen/RISCV/GlobalISel/combine.ll

+4-12
Original file line numberDiff line numberDiff line change
@@ -42,18 +42,10 @@ define i32 @mul_to_shift(i32 %x) {
4242
; RV32-NEXT: slli a0, a0, 2
4343
; RV32-NEXT: ret
4444
;
45-
; RV64-O0-LABEL: mul_to_shift:
46-
; RV64-O0: # %bb.0:
47-
; RV64-O0-NEXT: li a1, 2
48-
; RV64-O0-NEXT: sll a0, a0, a1
49-
; RV64-O0-NEXT: ret
50-
;
51-
; RV64-OPT-LABEL: mul_to_shift:
52-
; RV64-OPT: # %bb.0:
53-
; RV64-OPT-NEXT: slli a0, a0, 2
54-
; RV64-OPT-NEXT: ret
45+
; RV64-LABEL: mul_to_shift:
46+
; RV64: # %bb.0:
47+
; RV64-NEXT: slli a0, a0, 2
48+
; RV64-NEXT: ret
5549
%a = mul i32 %x, 4
5650
ret i32 %a
5751
}
58-
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
59-
; RV64: {{.*}}

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant64.mir

+8-54
Original file line numberDiff line numberDiff line change
@@ -141,9 +141,8 @@ body: |
141141
; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 524288
142142
; CHECK-NEXT: $x10 = COPY [[LUI]]
143143
; CHECK-NEXT: PseudoRET implicit $x10
144-
%0:gprb(s32) = G_CONSTANT i32 -2147483648
145-
%1:gprb(s64) = G_ANYEXT %0(s32)
146-
$x10 = COPY %1(s64)
144+
%0:gprb(s64) = G_CONSTANT i64 -2147483648
145+
$x10 = COPY %0(s64)
147146
PseudoRET implicit $x10
148147
149148
...
@@ -163,9 +162,8 @@ body: |
163162
; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LUI]], 648
164163
; CHECK-NEXT: $x10 = COPY [[ADDIW]]
165164
; CHECK-NEXT: PseudoRET implicit $x10
166-
%0:gprb(s32) = G_CONSTANT i32 -2147483000
167-
%1:gprb(s64) = G_ANYEXT %0(s32)
168-
$x10 = COPY %1(s64)
165+
%0:gprb(s64) = G_CONSTANT i64 -2147483000
166+
$x10 = COPY %0(s64)
169167
PseudoRET implicit $x10
170168
171169
...
@@ -185,9 +183,8 @@ body: |
185183
; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LUI]], -1
186184
; CHECK-NEXT: $x10 = COPY [[ADDIW]]
187185
; CHECK-NEXT: PseudoRET implicit $x10
188-
%0:gprb(s32) = G_CONSTANT i32 2147483647
189-
%1:gprb(s64) = G_ANYEXT %0(s32)
190-
$x10 = COPY %1(s64)
186+
%0:gprb(s64) = G_CONSTANT i64 2147483647
187+
$x10 = COPY %0(s64)
191188
PseudoRET implicit $x10
192189
193190
...
@@ -207,51 +204,8 @@ body: |
207204
; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LUI]], -648
208205
; CHECK-NEXT: $x10 = COPY [[ADDIW]]
209206
; CHECK-NEXT: PseudoRET implicit $x10
210-
%0:gprb(s32) = G_CONSTANT i32 2147483000
211-
%1:gprb(s64) = G_ANYEXT %0(s32)
212-
$x10 = COPY %1(s64)
213-
PseudoRET implicit $x10
214-
215-
...
216-
---
217-
name: const_i32_256
218-
legalized: true
219-
regBankSelected: true
220-
tracksRegLiveness: true
221-
body: |
222-
bb.0:
223-
liveins: $x10
224-
225-
; CHECK-LABEL: name: const_i32_256
226-
; CHECK: liveins: $x10
227-
; CHECK-NEXT: {{ $}}
228-
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 256
229-
; CHECK-NEXT: $x10 = COPY [[ADDI]]
230-
; CHECK-NEXT: PseudoRET implicit $x10
231-
%0:gprb(s32) = G_CONSTANT i32 256
232-
%1:gprb(s64) = G_ANYEXT %0(s32)
233-
$x10 = COPY %1(s64)
234-
PseudoRET implicit $x10
235-
236-
...
237-
---
238-
name: const_i32_0
239-
legalized: true
240-
regBankSelected: true
241-
tracksRegLiveness: true
242-
body: |
243-
bb.0:
244-
liveins: $x10
245-
246-
; CHECK-LABEL: name: const_i32_0
247-
; CHECK: liveins: $x10
248-
; CHECK-NEXT: {{ $}}
249-
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
250-
; CHECK-NEXT: $x10 = COPY [[COPY]]
251-
; CHECK-NEXT: PseudoRET implicit $x10
252-
%0:gprb(s32) = G_CONSTANT i32 0
253-
%1:gprb(s64) = G_ANYEXT %0(s32)
254-
$x10 = COPY %1(s64)
207+
%0:gprb(s64) = G_CONSTANT i64 2147483000
208+
$x10 = COPY %0(s64)
255209
PseudoRET implicit $x10
256210
257211
...

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/sext-rv64.mir

+10-5
Original file line numberDiff line numberDiff line change
@@ -7,13 +7,18 @@ regBankSelected: true
77
tracksRegLiveness: true
88
body: |
99
bb.0:
10+
liveins: $x10
11+
1012
; CHECK-LABEL: name: sext_32_64
11-
; CHECK: [[LUI:%[0-9]+]]:gpr = LUI 524288
12-
; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LUI]], 0
13+
; CHECK: liveins: $x10
14+
; CHECK-NEXT: {{ $}}
15+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
16+
; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[COPY]], 0
1317
; CHECK-NEXT: $x8 = COPY [[ADDIW]]
14-
%0:gprb(s32) = G_CONSTANT i32 -2147483648
15-
%1:gprb(s64) = G_SEXT %0
16-
$x8 = COPY %1(s64)
18+
%0:gprb(s64) = COPY $x10
19+
%1:gprb(s32) = G_TRUNC %0
20+
%2:gprb(s64) = G_SEXT %1
21+
$x8 = COPY %2(s64)
1722
...
1823
---
1924
name: sext_inreg_64_32

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/shift-rv64.mir

-25
Original file line numberDiff line numberDiff line change
@@ -26,31 +26,6 @@ body: |
2626
PseudoRET implicit $x10
2727
...
2828

29-
---
30-
name: shl_zext
31-
legalized: true
32-
regBankSelected: true
33-
tracksRegLiveness: true
34-
body: |
35-
bb.0:
36-
liveins: $x10
37-
38-
; CHECK-LABEL: name: shl_zext
39-
; CHECK: liveins: $x10
40-
; CHECK-NEXT: {{ $}}
41-
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
42-
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
43-
; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[ADDI]]
44-
; CHECK-NEXT: $x10 = COPY [[SLL]]
45-
; CHECK-NEXT: PseudoRET implicit $x10
46-
%0:gprb(s64) = COPY $x10
47-
%1:gprb(s32) = G_CONSTANT i32 1
48-
%2:gprb(s64) = G_ZEXT %1
49-
%3:gprb(s64) = G_SHL %0, %2(s64)
50-
$x10 = COPY %3(s64)
51-
PseudoRET implicit $x10
52-
...
53-
5429
---
5530
name: shl_and
5631
legalized: true

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zext-rv64.mir

+14-7
Original file line numberDiff line numberDiff line change
@@ -8,17 +8,24 @@ regBankSelected: true
88
tracksRegLiveness: true
99
body: |
1010
bb.0:
11+
liveins: $x10
12+
1113
; CHECK-LABEL: name: zext_32_64
12-
; CHECK: [[LUI:%[0-9]+]]:gpr = LUI 524288
13-
; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[LUI]], 32
14+
; CHECK: liveins: $x10
15+
; CHECK-NEXT: {{ $}}
16+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
17+
; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 32
1418
; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[SLLI]], 32
1519
; CHECK-NEXT: $x8 = COPY [[SRLI]]
1620
;
1721
; ZBA-LABEL: name: zext_32_64
18-
; ZBA: [[LUI:%[0-9]+]]:gpr = LUI 524288
19-
; ZBA-NEXT: [[ADD_UW:%[0-9]+]]:gpr = ADD_UW [[LUI]], $x0
22+
; ZBA: liveins: $x10
23+
; ZBA-NEXT: {{ $}}
24+
; ZBA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
25+
; ZBA-NEXT: [[ADD_UW:%[0-9]+]]:gpr = ADD_UW [[COPY]], $x0
2026
; ZBA-NEXT: $x8 = COPY [[ADD_UW]]
21-
%0:gprb(s32) = G_CONSTANT i32 -2147483648
22-
%1:gprb(s64) = G_ZEXT %0
23-
$x8 = COPY %1(s64)
27+
%0:gprb(s64) = COPY $x10
28+
%1:gprb(s32) = G_TRUNC %0
29+
%2:gprb(s64) = G_ZEXT %1
30+
$x8 = COPY %2(s64)
2431
...

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir

+15-21
Original file line numberDiff line numberDiff line change
@@ -11,18 +11,16 @@ body: |
1111
; RV64I-LABEL: name: abs_i8
1212
; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
1313
; RV64I-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 8
14-
; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
15-
; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32)
16-
; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
17-
; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]]
18-
; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
19-
; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ASSERT_ZEXT]], [[C2]](s64)
20-
; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C2]](s64)
21-
; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[AND]](s64)
14+
; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
15+
; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
16+
; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ASSERT_ZEXT]], [[C1]](s64)
17+
; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C1]](s64)
18+
; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C]](s64)
2219
; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASSERT_ZEXT]], [[ASHR1]]
2320
; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ADD]], [[ASHR1]]
24-
; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C1]]
25-
; RV64I-NEXT: $x10 = COPY [[AND1]](s64)
21+
; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
22+
; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C2]]
23+
; RV64I-NEXT: $x10 = COPY [[AND]](s64)
2624
; RV64I-NEXT: PseudoRET implicit $x10
2725
;
2826
; RV64ZBB-LABEL: name: abs_i8
@@ -51,16 +49,13 @@ body: |
5149
; RV64I-LABEL: name: abs_i16
5250
; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
5351
; RV64I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 16
54-
; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
55-
; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32)
56-
; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
57-
; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]]
58-
; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[ASSERT_SEXT]], [[AND]](s64)
52+
; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
53+
; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[ASSERT_SEXT]], [[C]](s64)
5954
; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASSERT_SEXT]], [[ASHR]]
6055
; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ADD]], [[ASHR]]
61-
; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
62-
; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[XOR]], [[C2]](s64)
63-
; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C2]](s64)
56+
; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
57+
; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[XOR]], [[C1]](s64)
58+
; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C1]](s64)
6459
; RV64I-NEXT: $x10 = COPY [[ASHR1]](s64)
6560
; RV64I-NEXT: PseudoRET implicit $x10
6661
;
@@ -88,9 +83,8 @@ body: |
8883
; RV64I-LABEL: name: abs_i32
8984
; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
9085
; RV64I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 32
91-
; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
92-
; RV64I-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32)
93-
; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[ASSERT_SEXT]], [[ZEXT]](s64)
86+
; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
87+
; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[ASSERT_SEXT]], [[C]](s64)
9488
; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASSERT_SEXT]], [[ASHR]]
9589
; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ADD]], [[ASHR]]
9690
; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[XOR]], 32

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