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[RISCV][GISel] Add missing tests for G_CTLZ/CTTZ instruction selection. NFC
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \
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# RUN: -simplify-mir -verify-machineinstrs %s -o - \
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# RUN: | FileCheck -check-prefix=RV32I %s
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---
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name: ctlz_s32
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legalized: true
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regBankSelected: true
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body: |
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bb.0.entry:
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; RV32I-LABEL: name: ctlz_s32
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; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x10
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; RV32I-NEXT: [[CLZ:%[0-9]+]]:gpr = CLZ [[COPY]]
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; RV32I-NEXT: $x10 = COPY [[CLZ]]
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; RV32I-NEXT: PseudoRET implicit $x10
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%0:gprb(s32) = COPY $x10
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%1:gprb(s32) = G_CTLZ %0
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$x10 = COPY %1(s32)
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PseudoRET implicit $x10
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...
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=instruction-select \
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# RUN: -simplify-mir -verify-machineinstrs %s -o - \
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# RUN: | FileCheck -check-prefix=RV64I %s
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---
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name: ctlz_s32
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legalized: true
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regBankSelected: true
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body: |
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bb.0.entry:
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; RV64I-LABEL: name: ctlz_s32
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; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x10
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; RV64I-NEXT: [[CLZW:%[0-9]+]]:gpr = CLZW [[COPY]]
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; RV64I-NEXT: $x10 = COPY [[CLZW]]
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; RV64I-NEXT: PseudoRET implicit $x10
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%0:gprb(s64) = COPY $x10
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%1:gprb(s32) = G_TRUNC %0
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%2:gprb(s32) = G_CTLZ %1
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%3:gprb(s64) = G_ANYEXT %2
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$x10 = COPY %3(s64)
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PseudoRET implicit $x10
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...
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---
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name: ctlz_s64
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legalized: true
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regBankSelected: true
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body: |
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bb.0.entry:
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; RV64I-LABEL: name: ctlz_s64
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; RV64I: [[CLZ:%[0-9]+]]:gpr = CLZ [[CLZ]]
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; RV64I-NEXT: $x10 = COPY [[CLZ]]
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; RV64I-NEXT: PseudoRET implicit $x10
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%0:gprb(s64) = COPY $x10
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%1:gprb(s64) = G_CTLZ %1
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$x10 = COPY %1(s64)
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PseudoRET implicit $x10
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...
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \
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# RUN: -simplify-mir -verify-machineinstrs %s -o - \
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# RUN: | FileCheck -check-prefix=RV32I %s
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---
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name: cttz_s32
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legalized: true
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regBankSelected: true
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body: |
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bb.0.entry:
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; RV32I-LABEL: name: cttz_s32
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; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x10
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; RV32I-NEXT: [[CTZ:%[0-9]+]]:gpr = CTZ [[COPY]]
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; RV32I-NEXT: $x10 = COPY [[CTZ]]
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; RV32I-NEXT: PseudoRET implicit $x10
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%0:gprb(s32) = COPY $x10
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%1:gprb(s32) = G_CTTZ %0
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$x10 = COPY %1(s32)
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PseudoRET implicit $x10
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...
Lines changed: 40 additions & 0 deletions
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=instruction-select \
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# RUN: -simplify-mir -verify-machineinstrs %s -o - \
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# RUN: | FileCheck -check-prefix=RV64I %s
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---
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name: cttz_s32
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legalized: true
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regBankSelected: true
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body: |
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bb.0.entry:
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; RV64I-LABEL: name: cttz_s32
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; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x10
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; RV64I-NEXT: [[CTZW:%[0-9]+]]:gpr = CTZW [[COPY]]
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; RV64I-NEXT: $x10 = COPY [[CTZW]]
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; RV64I-NEXT: PseudoRET implicit $x10
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%0:gprb(s64) = COPY $x10
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%1:gprb(s32) = G_TRUNC %0
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%2:gprb(s32) = G_CTTZ %1
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%3:gprb(s64) = G_ANYEXT %2
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$x10 = COPY %3(s64)
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PseudoRET implicit $x10
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...
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---
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name: cttz_s64
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legalized: true
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regBankSelected: true
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body: |
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bb.0.entry:
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; RV64I-LABEL: name: cttz_s64
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; RV64I: [[CTZ:%[0-9]+]]:gpr = CTZ [[CTZ]]
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; RV64I-NEXT: $x10 = COPY [[CTZ]]
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; RV64I-NEXT: PseudoRET implicit $x10
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%0:gprb(s64) = COPY $x10
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%1:gprb(s64) = G_CTTZ %1
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$x10 = COPY %1(s64)
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PseudoRET implicit $x10
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...

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