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[ELF] Pass Ctx & to Arch/
1 parent 37ce3c2 commit 6d03a69

18 files changed

+145
-141
lines changed

‎lld/ELF/Arch/AArch64.cpp

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -91,9 +91,10 @@ class AArch64 : public TargetInfo {
9191
};
9292

9393
struct AArch64Relaxer {
94+
Ctx &ctx;
9495
bool safeToRelaxAdrpLdr = false;
9596

96-
AArch64Relaxer(ArrayRef<Relocation> relocs);
97+
AArch64Relaxer(Ctx &ctx, ArrayRef<Relocation> relocs);
9798
bool tryRelaxAdrpAdd(const Relocation &adrpRel, const Relocation &addRel,
9899
uint64_t secAddr, uint8_t *buf) const;
99100
bool tryRelaxAdrpLdr(const Relocation &adrpRel, const Relocation &ldrRel,
@@ -750,7 +751,8 @@ void AArch64::relaxTlsIeToLe(uint8_t *loc, const Relocation &rel,
750751
llvm_unreachable("invalid relocation for TLS IE to LE relaxation");
751752
}
752753

753-
AArch64Relaxer::AArch64Relaxer(ArrayRef<Relocation> relocs) {
754+
AArch64Relaxer::AArch64Relaxer(Ctx &ctx, ArrayRef<Relocation> relocs)
755+
: ctx(ctx) {
754756
if (!ctx.arg.relax)
755757
return;
756758
// Check if R_AARCH64_ADR_GOT_PAGE and R_AARCH64_LD64_GOT_LO12_NC
@@ -909,7 +911,7 @@ void AArch64::relocateAlloc(InputSectionBase &sec, uint8_t *buf) const {
909911
secAddr += s->outSecOff;
910912
else if (auto *ehIn = dyn_cast<EhInputSection>(&sec))
911913
secAddr += ehIn->getParent()->outSecOff;
912-
AArch64Relaxer relaxer(sec.relocs());
914+
AArch64Relaxer relaxer(ctx, sec.relocs());
913915
for (size_t i = 0, size = sec.relocs().size(); i != size; ++i) {
914916
const Relocation &rel = sec.relocs()[i];
915917
uint8_t *loc = buf + rel.offset;
@@ -1149,13 +1151,13 @@ addTaggedSymbolReferences(InputSectionBase &sec,
11491151
// Ideally, this isn't a problem, as any TU that imports or exports tagged
11501152
// symbols should also be built with tagging. But, to handle these cases, we
11511153
// demote the symbol to be untagged.
1152-
void lld::elf::createTaggedSymbols(const SmallVector<ELFFileBase *, 0> &files) {
1154+
void elf::createTaggedSymbols(Ctx &ctx) {
11531155
assert(hasMemtag());
11541156

11551157
// First, collect all symbols that are marked as tagged, and count how many
11561158
// times they're marked as tagged.
11571159
DenseMap<Symbol *, unsigned> taggedSymbolReferenceCount;
1158-
for (InputFile* file : files) {
1160+
for (InputFile *file : ctx.objectFiles) {
11591161
if (file->kind() != InputFile::ObjKind)
11601162
continue;
11611163
for (InputSectionBase *section : file->getSections()) {
@@ -1171,7 +1173,7 @@ void lld::elf::createTaggedSymbols(const SmallVector<ELFFileBase *, 0> &files) {
11711173
// definitions to a symbol exceeds the amount of times they're marked as
11721174
// tagged, it means we have an objfile that uses the untagged variant of the
11731175
// symbol.
1174-
for (InputFile *file : files) {
1176+
for (InputFile *file : ctx.objectFiles) {
11751177
if (file->kind() != InputFile::BinaryKind &&
11761178
file->kind() != InputFile::ObjKind)
11771179
continue;

‎lld/ELF/Arch/ARM.cpp

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -214,7 +214,7 @@ void ARM::writeIgotPlt(uint8_t *buf, const Symbol &s) const {
214214

215215
// Long form PLT Header that does not have any restrictions on the displacement
216216
// of the .plt from the .got.plt.
217-
static void writePltHeaderLong(uint8_t *buf) {
217+
static void writePltHeaderLong(Ctx &ctx, uint8_t *buf) {
218218
write32(buf + 0, 0xe52de004); // str lr, [sp,#-4]!
219219
write32(buf + 4, 0xe59fe004); // ldr lr, L2
220220
write32(buf + 8, 0xe08fe00e); // L1: add lr, pc, lr
@@ -280,7 +280,7 @@ void ARM::writePltHeader(uint8_t *buf) const {
280280
uint64_t offset = ctx.in.gotPlt->getVA() - ctx.in.plt->getVA() - 4;
281281
if (!llvm::isUInt<27>(offset)) {
282282
// We cannot encode the Offset, use the long form.
283-
writePltHeaderLong(buf);
283+
writePltHeaderLong(ctx, buf);
284284
return;
285285
}
286286
write32(buf + 0, pltData[0]);
@@ -1048,7 +1048,7 @@ void elf::sortArmMappingSymbols() {
10481048
}
10491049
}
10501050

1051-
void elf::addArmInputSectionMappingSymbols() {
1051+
void elf::addArmInputSectionMappingSymbols(Ctx &ctx) {
10521052
// Collect mapping symbols for every executable input sections.
10531053
// The linker generated mapping symbols for all the synthetic
10541054
// sections are adding into the sectionmap through the function
@@ -1327,7 +1327,7 @@ class elf::ArmCmseSGVeneer {
13271327
const std::optional<uint64_t> entAddr;
13281328
};
13291329

1330-
ArmCmseSGSection::ArmCmseSGSection()
1330+
ArmCmseSGSection::ArmCmseSGSection(Ctx &ctx)
13311331
: SyntheticSection(llvm::ELF::SHF_ALLOC | llvm::ELF::SHF_EXECINSTR,
13321332
llvm::ELF::SHT_PROGBITS,
13331333
/*alignment=*/32, ".gnu.sgstubs") {
@@ -1440,7 +1440,7 @@ void ArmCmseSGSection::finalizeContents(Ctx &) {
14401440
// in the executable output by this link.
14411441
// See Arm® v8-M Security Extensions: Requirements on Development Tools
14421442
// https://developer.arm.com/documentation/ecm0359818/latest
1443-
template <typename ELFT> void elf::writeARMCmseImportLib() {
1443+
template <typename ELFT> void elf::writeARMCmseImportLib(Ctx &ctx) {
14441444
StringTableSection *shstrtab =
14451445
make<StringTableSection>(".shstrtab", /*dynamic=*/false);
14461446
StringTableSection *strtab =
@@ -1538,10 +1538,10 @@ TargetInfo *elf::getARMTargetInfo(Ctx &ctx) {
15381538
return &target;
15391539
}
15401540

1541-
template void elf::writeARMCmseImportLib<ELF32LE>();
1542-
template void elf::writeARMCmseImportLib<ELF32BE>();
1543-
template void elf::writeARMCmseImportLib<ELF64LE>();
1544-
template void elf::writeARMCmseImportLib<ELF64BE>();
1541+
template void elf::writeARMCmseImportLib<ELF32LE>(Ctx &);
1542+
template void elf::writeARMCmseImportLib<ELF32BE>(Ctx &);
1543+
template void elf::writeARMCmseImportLib<ELF64LE>(Ctx &);
1544+
template void elf::writeARMCmseImportLib<ELF64BE>(Ctx &);
15451545

15461546
template void ObjFile<ELF32LE>::importCmseSymbols();
15471547
template void ObjFile<ELF32BE>::importCmseSymbols();

‎lld/ELF/Arch/LoongArch.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -212,7 +212,7 @@ LoongArch::LoongArch(Ctx &ctx) : TargetInfo(ctx) {
212212
ipltEntrySize = 16;
213213
}
214214

215-
static uint32_t getEFlags(const InputFile *f) {
215+
static uint32_t getEFlags(Ctx &ctx, const InputFile *f) {
216216
if (ctx.arg.is64)
217217
return cast<ObjFile<ELF64LE>>(f)->getObj().getHeader().e_flags;
218218
return cast<ObjFile<ELF32LE>>(f)->getObj().getHeader().e_flags;
@@ -242,7 +242,7 @@ uint32_t LoongArch::calcEFlags() const {
242242
continue;
243243

244244
// Take the first non-zero e_flags as the reference.
245-
uint32_t flags = getEFlags(f);
245+
uint32_t flags = getEFlags(ctx, f);
246246
if (target == 0 && flags != 0) {
247247
target = flags;
248248
targetFile = f;
@@ -825,7 +825,7 @@ bool LoongArch::relaxOnce(int pass) const {
825825
return false;
826826

827827
if (pass == 0)
828-
initSymbolAnchors();
828+
initSymbolAnchors(ctx);
829829

830830
SmallVector<InputSection *, 0> storage;
831831
bool changed = false;

‎lld/ELF/Arch/Mips.cpp

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@ template <class ELFT> MIPS<ELFT>::MIPS(Ctx &ctx) : TargetInfo(ctx) {
7070
}
7171

7272
template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const {
73-
return calcMipsEFlags<ELFT>();
73+
return calcMipsEFlags<ELFT>(ctx);
7474
}
7575

7676
template <class ELFT>
@@ -262,14 +262,14 @@ template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *buf) const {
262262
// Overwrite trap instructions written by Writer::writeTrapInstr.
263263
memset(buf, 0, pltHeaderSize);
264264

265-
write16(buf, isMipsR6() ? 0x7860 : 0x7980); // addiupc v1, (GOTPLT) - .
265+
write16(buf, isMipsR6(ctx) ? 0x7860 : 0x7980); // addiupc v1, (GOTPLT) - .
266266
write16(buf + 4, 0xff23); // lw $25, 0($3)
267267
write16(buf + 8, 0x0535); // subu16 $2, $2, $3
268268
write16(buf + 10, 0x2525); // srl16 $2, $2, 2
269269
write16(buf + 12, 0x3302); // addiu $24, $2, -2
270270
write16(buf + 14, 0xfffe);
271271
write16(buf + 16, 0x0dff); // move $15, $31
272-
if (isMipsR6()) {
272+
if (isMipsR6(ctx)) {
273273
write16(buf + 18, 0x0f83); // move $28, $3
274274
write16(buf + 20, 0x472b); // jalrc $25
275275
write16(buf + 22, 0x0c00); // nop
@@ -324,7 +324,7 @@ void MIPS<ELFT>::writePlt(uint8_t *buf, const Symbol &sym,
324324
// Overwrite trap instructions written by Writer::writeTrapInstr.
325325
memset(buf, 0, pltEntrySize);
326326

327-
if (isMipsR6()) {
327+
if (isMipsR6(ctx)) {
328328
write16(buf, 0x7840); // addiupc $2, (GOTPLT) - .
329329
write16(buf + 4, 0xff22); // lw $25, 0($2)
330330
write16(buf + 8, 0x0f02); // move $24, $2
@@ -341,8 +341,9 @@ void MIPS<ELFT>::writePlt(uint8_t *buf, const Symbol &sym,
341341
}
342342

343343
uint32_t loadInst = ELFT::Is64Bits ? 0xddf90000 : 0x8df90000;
344-
uint32_t jrInst = isMipsR6() ? (ctx.arg.zHazardplt ? 0x03200409 : 0x03200009)
345-
: (ctx.arg.zHazardplt ? 0x03200408 : 0x03200008);
344+
uint32_t jrInst = isMipsR6(ctx)
345+
? (ctx.arg.zHazardplt ? 0x03200409 : 0x03200009)
346+
: (ctx.arg.zHazardplt ? 0x03200408 : 0x03200008);
346347
uint32_t addInst = ELFT::Is64Bits ? 0x65f80000 : 0x25f80000;
347348

348349
write32(buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry)

‎lld/ELF/Arch/MipsArchTree.cpp

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -62,7 +62,7 @@ static StringRef getNanName(bool isNan2008) {
6262

6363
static StringRef getFpName(bool isFp64) { return isFp64 ? "64" : "32"; }
6464

65-
static void checkFlags(ArrayRef<FileFlags> files) {
65+
static void checkFlags(Ctx &ctx, ArrayRef<FileFlags> files) {
6666
assert(!files.empty() && "expected non-empty file list");
6767

6868
uint32_t abi = files[0].flags & (EF_MIPS_ABI | EF_MIPS_ABI2);
@@ -293,7 +293,7 @@ static uint32_t getArchFlags(ArrayRef<FileFlags> files) {
293293
return ret;
294294
}
295295

296-
template <class ELFT> uint32_t elf::calcMipsEFlags() {
296+
template <class ELFT> uint32_t elf::calcMipsEFlags(Ctx &ctx) {
297297
std::vector<FileFlags> v;
298298
for (InputFile *f : ctx.objectFiles)
299299
v.push_back({f, cast<ObjFile<ELFT>>(f)->getObj().getHeader().e_flags});
@@ -305,7 +305,7 @@ template <class ELFT> uint32_t elf::calcMipsEFlags() {
305305
return 0;
306306
return ctx.arg.mipsN32Abi ? EF_MIPS_ABI2 : EF_MIPS_ABI_O32;
307307
}
308-
checkFlags(v);
308+
checkFlags(ctx, v);
309309
return getMiscFlags(v) | getPicFlags(v) | getArchFlags(v);
310310
}
311311

@@ -360,13 +360,13 @@ uint8_t elf::getMipsFpAbiFlag(uint8_t oldFlag, uint8_t newFlag,
360360
return oldFlag;
361361
}
362362

363-
template <class ELFT> static bool isN32Abi(const InputFile *f) {
364-
if (auto *ef = dyn_cast<ELFFileBase>(f))
363+
template <class ELFT> static bool isN32Abi(const InputFile &f) {
364+
if (auto *ef = dyn_cast<ELFFileBase>(&f))
365365
return ef->template getObj<ELFT>().getHeader().e_flags & EF_MIPS_ABI2;
366366
return false;
367367
}
368368

369-
bool elf::isMipsN32Abi(const InputFile *f) {
369+
bool elf::isMipsN32Abi(Ctx &ctx, const InputFile &f) {
370370
switch (ctx.arg.ekind) {
371371
case ELF32LEKind:
372372
return isN32Abi<ELF32LE>(f);
@@ -383,12 +383,12 @@ bool elf::isMipsN32Abi(const InputFile *f) {
383383

384384
bool elf::isMicroMips() { return ctx.arg.eflags & EF_MIPS_MICROMIPS; }
385385

386-
bool elf::isMipsR6() {
386+
bool elf::isMipsR6(Ctx &ctx) {
387387
uint32_t arch = ctx.arg.eflags & EF_MIPS_ARCH;
388388
return arch == EF_MIPS_ARCH_32R6 || arch == EF_MIPS_ARCH_64R6;
389389
}
390390

391-
template uint32_t elf::calcMipsEFlags<ELF32LE>();
392-
template uint32_t elf::calcMipsEFlags<ELF32BE>();
393-
template uint32_t elf::calcMipsEFlags<ELF64LE>();
394-
template uint32_t elf::calcMipsEFlags<ELF64BE>();
391+
template uint32_t elf::calcMipsEFlags<ELF32LE>(Ctx &);
392+
template uint32_t elf::calcMipsEFlags<ELF32BE>(Ctx &);
393+
template uint32_t elf::calcMipsEFlags<ELF64LE>(Ctx &);
394+
template uint32_t elf::calcMipsEFlags<ELF64BE>(Ctx &);

‎lld/ELF/Arch/PPC.cpp

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -64,15 +64,15 @@ class PPC final : public TargetInfo {
6464
static uint16_t lo(uint32_t v) { return v; }
6565
static uint16_t ha(uint32_t v) { return (v + 0x8000) >> 16; }
6666

67-
static uint32_t readFromHalf16(const uint8_t *loc) {
67+
static uint32_t readFromHalf16(Ctx &ctx, const uint8_t *loc) {
6868
return read32(ctx.arg.isLE ? loc : loc - 2);
6969
}
7070

71-
static void writeFromHalf16(uint8_t *loc, uint32_t insn) {
71+
static void writeFromHalf16(Ctx &ctx, uint8_t *loc, uint32_t insn) {
7272
write32(ctx.arg.isLE ? loc : loc - 2, insn);
7373
}
7474

75-
void elf::writePPC32GlinkSection(uint8_t *buf, size_t numEntries) {
75+
void elf::writePPC32GlinkSection(Ctx &ctx, uint8_t *buf, size_t numEntries) {
7676
// Create canonical PLT entries for non-PIE code. Compilers don't generate
7777
// non-GOT-non-PLT relocations referencing external functions for -fpie/-fPIE.
7878
uint32_t glink = ctx.in.plt->getVA(); // VA of .glink
@@ -412,8 +412,8 @@ void PPC::relaxTlsGdToIe(uint8_t *loc, const Relocation &rel,
412412
switch (rel.type) {
413413
case R_PPC_GOT_TLSGD16: {
414414
// addi rT, rA, x@got@tlsgd --> lwz rT, x@got@tprel(rA)
415-
uint32_t insn = readFromHalf16(loc);
416-
writeFromHalf16(loc, 0x80000000 | (insn & 0x03ff0000));
415+
uint32_t insn = readFromHalf16(ctx, loc);
416+
writeFromHalf16(ctx, loc, 0x80000000 | (insn & 0x03ff0000));
417417
relocateNoSym(loc, R_PPC_GOT_TPREL16, val);
418418
break;
419419
}
@@ -431,7 +431,7 @@ void PPC::relaxTlsGdToLe(uint8_t *loc, const Relocation &rel,
431431
switch (rel.type) {
432432
case R_PPC_GOT_TLSGD16:
433433
// addi r3, r31, x@got@tlsgd --> addis r3, r2, x@tprel@ha
434-
writeFromHalf16(loc, 0x3c620000 | ha(val));
434+
writeFromHalf16(ctx, loc, 0x3c620000 | ha(val));
435435
break;
436436
case R_PPC_TLSGD:
437437
// bl __tls_get_addr(x@tldgd) --> add r3, r3, x@tprel@l
@@ -447,7 +447,7 @@ void PPC::relaxTlsLdToLe(uint8_t *loc, const Relocation &rel,
447447
switch (rel.type) {
448448
case R_PPC_GOT_TLSLD16:
449449
// addi r3, rA, x@got@tlsgd --> addis r3, r2, 0
450-
writeFromHalf16(loc, 0x3c620000);
450+
writeFromHalf16(ctx, loc, 0x3c620000);
451451
break;
452452
case R_PPC_TLSLD:
453453
// r3+x@dtprel computes r3+x-0x8000, while we want it to compute r3+x@tprel
@@ -471,8 +471,8 @@ void PPC::relaxTlsIeToLe(uint8_t *loc, const Relocation &rel,
471471
switch (rel.type) {
472472
case R_PPC_GOT_TPREL16: {
473473
// lwz rT, x@got@tprel(rA) --> addis rT, r2, x@tprel@ha
474-
uint32_t rt = readFromHalf16(loc) & 0x03e00000;
475-
writeFromHalf16(loc, 0x3c020000 | rt | ha(val));
474+
uint32_t rt = readFromHalf16(ctx, loc) & 0x03e00000;
475+
writeFromHalf16(ctx, loc, 0x3c020000 | rt | ha(val));
476476
break;
477477
}
478478
case R_PPC_TLS: {

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