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[RISCV] Remove XSfcie extension.
This reverts 0d3eee3 and 4c37d30. XSfcie is not an official SiFive extension name. It stands for SiFive Custom Instruction Extension, which is mentioned in the S76 manual, but then elsewhere in the manual says it is not supported for S76. LLVM had various instructions and CSRs listed as part of this extension, but as far as SiFive is concerned, none of them are part of it. There are no documented extension names for these instructions and CSRs either externally or internally. If these are important to LLVM users, I can facilitate creating extension names for them and have them documented. For now I'm removing everything. Unfortunately, these instructions and CSRs are in LLVM 17 so this is an incompatible change.
1 parent 76facde commit 6dc5ba4

19 files changed

+23
-338
lines changed

‎clang/test/Driver/riscv-cpus.c

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -153,7 +153,6 @@
153153
// MCPU-SIFIVE-S76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
154154
// MCPU-SIFIVE-S76: "-target-feature" "+c"
155155
// MCPU-SIFIVE-S76: "-target-feature" "+zicsr" "-target-feature" "+zifencei" "-target-feature" "+zihintpause"
156-
// MCPU-SIFIVE-S76: "-target-feature" "+xsfcie"
157156
// MCPU-SIFIVE-S76: "-target-abi" "lp64d"
158157

159158
// mcpu with default march

‎clang/test/Preprocessor/riscv-target-features.c

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,6 @@
3333
// CHECK-NOT: __riscv_xcvmac {{.*$}}
3434
// CHECK-NOT: __riscv_xcvmem {{.*$}}
3535
// CHECK-NOT: __riscv_xcvsimd {{.*$}}
36-
// CHECK-NOT: __riscv_xsfcie {{.*$}}
3736
// CHECK-NOT: __riscv_xsfvcp {{.*$}}
3837
// CHECK-NOT: __riscv_xsfvfnrclipxfqf {{.*$}}
3938
// CHECK-NOT: __riscv_xsfvfwmaccqqq {{.*$}}
@@ -315,14 +314,6 @@
315314
// RUN: -o - | FileCheck --check-prefix=CHECK-XCVSIMD-EXT %s
316315
// CHECK-XCVSIMD-EXT: __riscv_xcvsimd 1000000{{$}}
317316

318-
// RUN: %clang --target=riscv32-unknown-linux-gnu \
319-
// RUN: -march=rv32ixsfcie -x c -E -dM %s \
320-
// RUN: -o - | FileCheck --check-prefix=CHECK-XSFCIE-EXT %s
321-
// RUN: %clang --target=riscv64-unknown-linux-gnu \
322-
// RUN: -march=rv64ixsfcie -x c -E -dM %s \
323-
// RUN: -o - | FileCheck --check-prefix=CHECK-XSFCIE-EXT %s
324-
// CHECK-XSFCIE-EXT: __riscv_xsfcie 1000000{{$}}
325-
326317
// RUN: %clang --target=riscv32-unknown-linux-gnu \
327318
// RUN: -march=rv32ixsfvcp -x c -E -dM %s \
328319
// RUN: -o - | FileCheck --check-prefix=CHECK-XSFVCP-EXT %s

‎llvm/docs/RISCVUsage.rst

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -300,9 +300,6 @@ The current vendor extensions supported are:
300300
``XCVbi``
301301
LLVM implements `version 1.0.0 of the CORE-V immediate branching custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/cv32e40p_v1.3.2/docs/source/instruction_set_extensions.rst>`_ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time.
302302

303-
``XSfcie``
304-
LLVM implements `version 1.0.0 of the SiFive Custom Instruction Extension (CIE) Software Specification <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive. All custom instruction are added as described in the specification, and the riscv-toolchain-convention document linked above. These instructions are only available for S76 processor at this time.
305-
306303
Experimental C Intrinsics
307304
=========================
308305

‎llvm/docs/ReleaseNotes.rst

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -146,6 +146,11 @@ Changes to the RISC-V Backend
146146
and is no longer experimental. However, the C intrinsics for these extensions
147147
are still experimental. To use the C intrinsics for these extensions,
148148
``-menable-experimental-extensions`` needs to be passed to Clang.
149+
* XSfcie extension and SiFive CSRs and instructions that were associated with
150+
it have been removed. None of these CSRs and instructions were part of
151+
"SiFive Custom Instruction Extension" as SiFive defines it. The LLVM project
152+
needs to work with SiFive to define and document real extension names for
153+
individual CSRs and instructions.
149154

150155
Changes to the WebAssembly Backend
151156
----------------------------------

‎llvm/lib/Support/RISCVISAInfo.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -75,7 +75,6 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
7575
{"xcvmac", RISCVExtensionVersion{1, 0}},
7676
{"xcvmem", RISCVExtensionVersion{1, 0}},
7777
{"xcvsimd", RISCVExtensionVersion{1, 0}},
78-
{"xsfcie", RISCVExtensionVersion{1, 0}},
7978
{"xsfvcp", RISCVExtensionVersion{1, 0}},
8079
{"xsfvfnrclipxfqf", RISCVExtensionVersion{1, 0}},
8180
{"xsfvfwmaccqqq", RISCVExtensionVersion{1, 0}},

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Lines changed: 3 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -1832,57 +1832,18 @@ ParseStatus RISCVAsmParser::parseCSRSystemRegister(OperandVector &Operands) {
18321832
if (getParser().parseIdentifier(Identifier))
18331833
return ParseStatus::Failure;
18341834

1835-
// Check for CSR names conflicts.
1836-
// Custom CSR names might conflict with CSR names in privileged spec.
1837-
// E.g. - SiFive mnscratch(0x350) and privileged spec mnscratch(0x740).
1838-
auto CheckCSRNameConflict = [&]() {
1839-
if (!(RISCVSysReg::lookupSysRegByName(Identifier))) {
1840-
Error(S, "system register use requires an option to be enabled");
1841-
return true;
1842-
}
1843-
return false;
1844-
};
1845-
1846-
// First check for vendor specific CSRs.
1847-
auto SiFiveReg = RISCVSysReg::lookupSiFiveRegByName(Identifier);
1848-
if (SiFiveReg) {
1849-
if (SiFiveReg->haveVendorRequiredFeatures(getSTI().getFeatureBits())) {
1850-
Operands.push_back(
1851-
RISCVOperand::createSysReg(Identifier, S, SiFiveReg->Encoding));
1852-
return ParseStatus::Success;
1853-
}
1854-
if (CheckCSRNameConflict())
1855-
return ParseStatus::Failure;
1856-
}
1857-
18581835
auto SysReg = RISCVSysReg::lookupSysRegByName(Identifier);
1836+
if (!SysReg)
1837+
SysReg = RISCVSysReg::lookupSysRegByAltName(Identifier);
18591838
if (!SysReg)
18601839
if ((SysReg = RISCVSysReg::lookupSysRegByDeprecatedName(Identifier)))
18611840
Warning(S, "'" + Identifier + "' is a deprecated alias for '" +
18621841
SysReg->Name + "'");
18631842

1864-
// Check for CSR encoding conflicts.
1865-
// Custom CSR encoding might conflict with CSR encoding in privileged spec.
1866-
// E.g. - SiFive mnscratch(0x350) and privileged spec miselect(0x350).
1867-
auto CheckCSREncodingConflict = [&]() {
1868-
auto Reg = RISCVSysReg::lookupSiFiveRegByEncoding(SysReg->Encoding);
1869-
if (Reg && Reg->haveVendorRequiredFeatures(getSTI().getFeatureBits())) {
1870-
Warning(S, "'" + Identifier + "' CSR is not available on the current " +
1871-
"subtarget. Instead '" + Reg->Name +
1872-
"' CSR will be used.");
1873-
Operands.push_back(
1874-
RISCVOperand::createSysReg(Reg->Name, S, Reg->Encoding));
1875-
return true;
1876-
}
1877-
return false;
1878-
};
1879-
1880-
// Accept a named SysReg if the required features are present.
1843+
// Accept a named Sys Reg if the required features are present.
18811844
if (SysReg) {
18821845
if (!SysReg->haveRequiredFeatures(getSTI().getFeatureBits()))
18831846
return Error(S, "system register use requires an option to be enabled");
1884-
if (CheckCSREncodingConflict())
1885-
return ParseStatus::Success;
18861847
Operands.push_back(
18871848
RISCVOperand::createSysReg(Identifier, S, SysReg->Encoding));
18881849
return ParseStatus::Success;

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -566,8 +566,6 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
566566
TRY_TO_DECODE_FEATURE(
567567
RISCV::FeatureVendorXSfvfnrclipxfqf, DecoderTableXSfvfnrclipxfqf32,
568568
"SiFive FP32-to-int8 Ranged Clip Instructions opcode table");
569-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcie, DecoderTableXSfcie32,
570-
"Sifive CIE custom opcode table");
571569
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
572570
DecoderTableXCVbitmanip32,
573571
"CORE-V Bit Manipulation custom opcode table");

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,6 @@ extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures];
2727

2828
namespace RISCVSysReg {
2929
#define GET_SysRegsList_IMPL
30-
#define GET_SiFiveRegsList_IMPL
3130
#include "RISCVGenSearchableTables.inc"
3231
} // namespace RISCVSysReg
3332

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

Lines changed: 1 addition & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -401,6 +401,7 @@ int getLoadFPImm(APFloat FPImm);
401401
namespace RISCVSysReg {
402402
struct SysReg {
403403
const char *Name;
404+
const char *AltName;
404405
const char *DeprecatedName;
405406
unsigned Encoding;
406407
// FIXME: add these additional fields when needed.
@@ -424,22 +425,9 @@ struct SysReg {
424425
return true;
425426
return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
426427
}
427-
428-
bool haveVendorRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
429-
// Not in 32-bit mode.
430-
if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
431-
return false;
432-
// No required feature associated with the system register.
433-
if (FeaturesRequired.none())
434-
return false;
435-
return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
436-
}
437428
};
438429

439-
struct SiFiveReg : SysReg {};
440-
441430
#define GET_SysRegsList_DECL
442-
#define GET_SiFiveRegsList_DECL
443431
#include "RISCVGenSearchableTables.inc"
444432
} // end namespace RISCVSysReg
445433

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -121,11 +121,8 @@ void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo,
121121
const MCSubtargetInfo &STI,
122122
raw_ostream &O) {
123123
unsigned Imm = MI->getOperand(OpNo).getImm();
124-
auto SiFiveReg = RISCVSysReg::lookupSiFiveRegByEncoding(Imm);
125124
auto SysReg = RISCVSysReg::lookupSysRegByEncoding(Imm);
126-
if (SiFiveReg && SiFiveReg->haveVendorRequiredFeatures(STI.getFeatureBits()))
127-
markup(O, Markup::Register) << SiFiveReg->Name;
128-
else if (SysReg && SysReg->haveRequiredFeatures(STI.getFeatureBits()))
125+
if (SysReg && SysReg->haveRequiredFeatures(STI.getFeatureBits()))
129126
markup(O, Markup::Register) << SysReg->Name;
130127
else
131128
markup(O, Markup::Register) << formatImm(Imm);

‎llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -826,13 +826,6 @@ def HasVendorXSfvcp : Predicate<"Subtarget->hasVendorXSfvcp()">,
826826
AssemblerPredicate<(all_of FeatureVendorXSfvcp),
827827
"'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)">;
828828

829-
def FeatureVendorXSfcie
830-
: SubtargetFeature<"xsfcie", "HasVendorXSfcie", "true",
831-
"'XSfcie' (SiFive Custom Instruction Extension SCIE.)">;
832-
def HasVendorXSfcie : Predicate<"Subtarget->hasVendorXSfcie()">,
833-
AssemblerPredicate<(all_of FeatureVendorXSfcie),
834-
"'XSfcie' (SiFive Custom Instruction Extension SCIE.)">;
835-
836829
def FeatureVendorXSfvqmaccdod
837830
: SubtargetFeature<"xsfvqmaccdod", "HasVendorXSfvqmaccdod", "true",
838831
"'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))",

‎llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td

Lines changed: 0 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -673,27 +673,3 @@ let Predicates = [HasVendorXSfvfnrclipxfqf] in {
673673
defm : VPatVFNRCLIP<"vfnrclip_xu_f_qf", "VFNRCLIP_XU_F_QF">;
674674
defm : VPatVFNRCLIP<"vfnrclip_x_f_qf", "VFNRCLIP_X_F_QF">;
675675
}
676-
677-
let Predicates = [HasVendorXSfcie] in {
678-
let hasSideEffects = 1, mayLoad = 0, mayStore = 0, DecoderNamespace = "XSfcie" in {
679-
def SF_CFLUSH_D_L1 : RVInstI<0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1), "cflush.d.l1","$rs1">,
680-
Sched<[]> {
681-
let rd = 0;
682-
let imm12 = {0b1111,0b1100,0b0000};
683-
}
684-
685-
def SF_CDISCARD_D_L1 : RVInstI<0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1), "cdiscard.d.l1","$rs1">,
686-
Sched<[]> {
687-
let rd = 0;
688-
let imm12 = {0b1111,0b1100,0b0010};
689-
}
690-
691-
def SF_CEASE : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "cease","">, Sched<[]> {
692-
let rs1 = 0;
693-
let rd = 0;
694-
let imm12 = {0b0011,0b0000,0b0101};
695-
}
696-
}
697-
def : InstAlias<"cflush.d.l1", (SF_CFLUSH_D_L1 X0)>;
698-
def : InstAlias<"cdiscard.d.l1", (SF_CDISCARD_D_L1 X0)>;
699-
} // Predicates = [HasVendorXScie]

‎llvm/lib/Target/RISCV/RISCVProcessors.td

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -174,8 +174,7 @@ def SIFIVE_S76 : RISCVProcessorModel<"sifive-s76",
174174
FeatureStdExtF,
175175
FeatureStdExtD,
176176
FeatureStdExtC,
177-
FeatureStdExtZihintpause,
178-
FeatureVendorXSfcie],
177+
FeatureStdExtZihintpause],
179178
[TuneSiFive7]>;
180179

181180
def SIFIVE_U54 : RISCVProcessorModel<"sifive-u54",

‎llvm/lib/Target/RISCV/RISCVSystemOperands.td

Lines changed: 12 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -19,9 +19,11 @@ include "llvm/TableGen/SearchableTable.td"
1919

2020
class SysReg<string name, bits<12> op> {
2121
string Name = name;
22-
// A maximum of one deprecated name is supported right now. It generates a
23-
// diagnostic when the name is used to encourage software to migrate away from
24-
// the name.
22+
// A maximum of one alias is supported right now.
23+
string AltName = name;
24+
// A maximum of one deprecated name is supported right now. Unlike the
25+
// `AltName` alias, a `DeprecatedName` generates a diagnostic when the name is
26+
// used to encourage software to migrate away from the name.
2527
string DeprecatedName = "";
2628
bits<12> Encoding = op;
2729
// FIXME: add these additional fields when needed.
@@ -41,7 +43,7 @@ def SysRegsList : GenericTable {
4143
let FilterClass = "SysReg";
4244
// FIXME: add "ReadWrite", "Mode", "Extra", "Number" fields when needed.
4345
let Fields = [
44-
"Name", "DeprecatedName", "Encoding", "FeaturesRequired",
46+
"Name", "AltName", "DeprecatedName", "Encoding", "FeaturesRequired",
4547
"isRV32Only",
4648
];
4749

@@ -54,32 +56,13 @@ def lookupSysRegByName : SearchIndex {
5456
let Key = [ "Name" ];
5557
}
5658

57-
def lookupSysRegByDeprecatedName : SearchIndex {
59+
def lookupSysRegByAltName : SearchIndex {
5860
let Table = SysRegsList;
59-
let Key = [ "DeprecatedName" ];
60-
}
61-
62-
class SiFiveReg<string name, bits<12> op> : SysReg<name, op>;
63-
64-
def SiFiveRegsList : GenericTable {
65-
let FilterClass = "SiFiveReg";
66-
// FIXME: add "ReadWrite", "Mode", "Extra", "Number" fields when needed.
67-
let Fields = [
68-
"Name", "DeprecatedName", "Encoding", "FeaturesRequired",
69-
"isRV32Only",
70-
];
71-
72-
let PrimaryKey = [ "Encoding" ];
73-
let PrimaryKeyName = "lookupSiFiveRegByEncoding";
61+
let Key = [ "AltName" ];
7462
}
7563

76-
def lookupSiFiveRegByName : SearchIndex {
77-
let Table = SiFiveRegsList;
78-
let Key = [ "Name" ];
79-
}
80-
81-
def lookupSiFiveRegByDeprecatedName : SearchIndex {
82-
let Table = SiFiveRegsList;
64+
def lookupSysRegByDeprecatedName : SearchIndex {
65+
let Table = SysRegsList;
8366
let Key = [ "DeprecatedName" ];
8467
}
8568

@@ -309,7 +292,7 @@ foreach i = 3...31 in
309292
//===----------------------------------------------------------------------===//
310293
// Machine Counter Setup
311294
//===----------------------------------------------------------------------===//
312-
let DeprecatedName = "mucounteren" in // Privileged spec v1.9.1 Name
295+
let AltName = "mucounteren" in // Privileged spec v1.9.1 Name
313296
def : SysReg<"mcountinhibit", 0x320>;
314297

315298
// mhpmevent3-mhpmevent31 at 0x323-0x33F.
@@ -322,20 +305,6 @@ foreach i = 3...31 in {
322305
def : SysReg<"mhpmevent"#i#"h", !add(0x723, !sub(i, 3))>;
323306
}
324307

325-
//===----------------------------------------------------------------------===//
326-
// SiFive Custom Machine Mode Registers
327-
//===----------------------------------------------------------------------===//
328-
329-
let FeaturesRequired = [{ {RISCV::FeatureVendorXSfcie} }] in {
330-
def : SiFiveReg<"mnscratch", 0x350>;
331-
def : SiFiveReg<"mnepc", 0x351>;
332-
def : SiFiveReg<"mncause", 0x352>;
333-
def : SiFiveReg<"mnstatus", 0x353>;
334-
def : SiFiveReg<"mbpm", 0x7C0>;
335-
def : SiFiveReg<"mfd", 0x7C1>;
336-
def : SiFiveReg<"mpd", 0x7C8>;
337-
}
338-
339308
//===----------------------------------------------------------------------===//
340309
// Debug/ Trace Registers (shared with Debug Mode)
341310
//===----------------------------------------------------------------------===//
@@ -353,7 +322,7 @@ def : SysReg<"dpc", 0x7B1>;
353322

354323
// "dscratch" is an alternative name for "dscratch0" which appeared in earlier
355324
// drafts of the RISC-V debug spec
356-
let DeprecatedName = "dscratch" in
325+
let AltName = "dscratch" in
357326
def : SysReg<"dscratch0", 0x7B2>;
358327
def : SysReg<"dscratch1", 0x7B3>;
359328

‎llvm/test/MC/RISCV/attribute-arch.s

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -282,9 +282,6 @@
282282
.attribute arch, "rv32i_zvfbfwma0p8"
283283
# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvfbfwma0p8_zvl32b1p0"
284284

285-
.attribute arch, "rv64i_xsfcie"
286-
# CHECK: attribute 5, "rv64i2p1_xsfcie1p0"
287-
288285
.attribute arch, "rv32izacas1p0"
289286
# CHECK: attribute 5, "rv32i2p1_a2p1_zacas1p0"
290287

‎llvm/test/MC/RISCV/machine-csr-names.s

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -9,9 +9,6 @@
99
# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
1010
# RUN: | llvm-objdump -d - \
1111
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
12-
#
13-
# RUN: llvm-mc -triple riscv32 %s 2>&1 | FileCheck -check-prefix CHECK-WARN %s
14-
# RUN: llvm-mc -triple riscv64 %s 2>&1 | FileCheck -check-prefix CHECK-WARN %s
1512

1613
##################################
1714
# Machine Information Registers
@@ -1495,8 +1492,6 @@ csrrs t1, dscratch, zero
14951492
# uimm12
14961493
csrrs t2, 0x7B2, zero
14971494

1498-
# CHECK-WARN: warning: 'dscratch' is a deprecated alias for 'dscratch0'
1499-
15001495
# dscratch1
15011496
# name
15021497
# CHECK-INST: csrrs t1, dscratch1, zero
@@ -1949,8 +1944,6 @@ csrrs t1, mucounteren, zero
19491944
# uimm12
19501945
csrrs t2, 0x320, zero
19511946

1952-
# CHECK-WARN: warning: 'mucounteren' is a deprecated alias for 'mcountinhibit'
1953-
19541947
# mhpmevent3
19551948
# name
19561949
# CHECK-INST: csrrs t1, mhpmevent3, zero

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