Skip to content

Commit 6e2a6e6

Browse files
davemgreendavemgreen
committed
Cleanup
1 parent d5a9cfe commit 6e2a6e6

13 files changed

+77
-115
lines changed

‎llvm/include/llvm/Analysis/MemoryLocation.h

Lines changed: 0 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -291,23 +291,12 @@ class MemoryLocation {
291291
return MemoryLocation(Ptr, LocationSize::beforeOrAfterPointer(), AATags);
292292
}
293293

294-
// TODO: Remove getSizeOrUnknown
295-
// interface once llvm/unittests/CodeGen/SelectionDAGAddressAnalysisTest is
296-
// updated
297-
static uint64_t getSizeOrUnknown(const TypeSize &T) {
298-
return T.isScalable() ? UnknownSize : T.getFixedValue();
299-
}
300-
301294
MemoryLocation() : Ptr(nullptr), Size(LocationSize::beforeOrAfterPointer()) {}
302295

303296
explicit MemoryLocation(const Value *Ptr, LocationSize Size,
304297
const AAMDNodes &AATags = AAMDNodes())
305298
: Ptr(Ptr), Size(Size), AATags(AATags) {}
306299

307-
explicit MemoryLocation(const Value *Ptr, TypeSize Size,
308-
const AAMDNodes &AATags = AAMDNodes())
309-
: Ptr(Ptr), Size(LocationSize::precise(Size)), AATags(AATags) {}
310-
311300
MemoryLocation getWithNewPtr(const Value *NewPtr) const {
312301
MemoryLocation Copy(*this);
313302
Copy.Ptr = NewPtr;

‎llvm/include/llvm/CodeGen/MachineFunction.h

Lines changed: 7 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1033,8 +1033,8 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
10331033
AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
10341034

10351035
MachineMemOperand *getMachineMemOperand(
1036-
MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, TypeSize ts,
1037-
Align base_alignment, const AAMDNodes &AAInfo = AAMDNodes(),
1036+
MachinePointerInfo PtrInfo, MachineMemOperand::Flags F, TypeSize TS,
1037+
Align BaseAlignment, const AAMDNodes &AAInfo = AAMDNodes(),
10381038
const MDNode *Ranges = nullptr, SyncScope::ID SSID = SyncScope::System,
10391039
AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
10401040
AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
@@ -1059,14 +1059,12 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
10591059
}
10601060

10611061
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
1062-
int64_t Offset, TypeSize ts) {
1062+
int64_t Offset, TypeSize TS) {
10631063
return getMachineMemOperand(
10641064
MMO, Offset,
1065-
ts.getKnownMinValue() == ~UINT64_C(0)
1066-
? LLT()
1067-
: ts.isScalable()
1068-
? LLT::scalable_vector(1, 8 * ts.getKnownMinValue())
1069-
: LLT::scalar(8 * ts.getKnownMinValue()));
1065+
TS.getKnownMinValue() == ~UINT64_C(0) ? LLT()
1066+
: TS.isScalable() ? LLT::scalable_vector(1, 8 * TS.getKnownMinValue())
1067+
: LLT::scalar(8 * TS.getKnownMinValue()));
10701068
}
10711069

10721070
/// getMachineMemOperand - Allocate a new MachineMemOperand by copying
@@ -1078,7 +1076,7 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
10781076
uint64_t Size);
10791077
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
10801078
const MachinePointerInfo &PtrInfo,
1081-
TypeSize ts);
1079+
TypeSize TS);
10821080
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
10831081
const MachinePointerInfo &PtrInfo,
10841082
LLT Ty);

‎llvm/include/llvm/CodeGen/MachineMemOperand.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -192,7 +192,7 @@ class MachineMemOperand {
192192
SyncScope::ID SSID = SyncScope::System,
193193
AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
194194
AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
195-
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, TypeSize ts,
195+
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, TypeSize TS,
196196
Align a, const AAMDNodes &AAInfo = AAMDNodes(),
197197
const MDNode *Ranges = nullptr,
198198
SyncScope::ID SSID = SyncScope::System,

‎llvm/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -82,9 +82,9 @@ class BaseIndexOffset {
8282
// Returns true `Op0` and `Op1` can be proven to alias/not alias, in
8383
// which case `IsAlias` is set to true/false.
8484
static bool computeAliasing(const SDNode *Op0,
85-
const std::optional<int64_t> NumBytes0,
85+
const std::optional<TypeSize> NumBytes0,
8686
const SDNode *Op1,
87-
const std::optional<int64_t> NumBytes1,
87+
const std::optional<TypeSize> NumBytes1,
8888
const SelectionDAG &DAG, bool &IsAlias);
8989

9090
/// Parses tree in N for base, index, offset addresses.

‎llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -220,7 +220,7 @@ bool GISelAddressing::instMayAlias(const MachineInstr &MI,
220220
// Default.
221221
return {false /*isvolatile*/,
222222
/*isAtomic*/ false, Register(),
223-
(int64_t)0 /*offset*/, TypeSize::getFixed(0) /*size*/,
223+
(int64_t)0 /*offset*/, TypeSize::Fixed(0) /*size*/,
224224
(MachineMemOperand *)nullptr};
225225
};
226226
MemUseCharacteristics MUC0 = getCharacteristics(&MI),
@@ -248,7 +248,7 @@ bool GISelAddressing::instMayAlias(const MachineInstr &MI,
248248
return false;
249249
}
250250

251-
// if NumBytes is scalable and offset is not 0, conservatively return may
251+
// If NumBytes is scalable and offset is not 0, conservatively return may
252252
// alias
253253
if ((MUC0.NumBytes.isScalable() && (MUC0.Offset != 0)) ||
254254
(MUC1.NumBytes.isScalable() && (MUC1.Offset != 0)))

‎llvm/lib/CodeGen/MachineFunction.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -493,12 +493,12 @@ MachineMemOperand *MachineFunction::getMachineMemOperand(
493493
}
494494

495495
MachineMemOperand *MachineFunction::getMachineMemOperand(
496-
MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, TypeSize ts,
497-
Align base_alignment, const AAMDNodes &AAInfo, const MDNode *Ranges,
496+
MachinePointerInfo PtrInfo, MachineMemOperand::Flags F, TypeSize TS,
497+
Align BaseAlignment, const AAMDNodes &AAInfo, const MDNode *Ranges,
498498
SyncScope::ID SSID, AtomicOrdering Ordering,
499499
AtomicOrdering FailureOrdering) {
500500
return new (Allocator)
501-
MachineMemOperand(PtrInfo, f, ts, base_alignment, AAInfo, Ranges, SSID,
501+
MachineMemOperand(PtrInfo, F, TS, BaseAlignment, AAInfo, Ranges, SSID,
502502
Ordering, FailureOrdering);
503503
}
504504

@@ -523,9 +523,9 @@ MachineMemOperand *MachineFunction::getMachineMemOperand(
523523
MachineMemOperand *
524524
MachineFunction::getMachineMemOperand(const MachineMemOperand *MMO,
525525
const MachinePointerInfo &PtrInfo,
526-
TypeSize ts) {
526+
TypeSize TS) {
527527
return new (Allocator)
528-
MachineMemOperand(PtrInfo, MMO->getFlags(), ts, MMO->getBaseAlign(),
528+
MachineMemOperand(PtrInfo, MMO->getFlags(), TS, MMO->getBaseAlign(),
529529
AAMDNodes(), nullptr, MMO->getSyncScopeID(),
530530
MMO->getSuccessOrdering(), MMO->getFailureOrdering());
531531
}

‎llvm/lib/CodeGen/MachineInstr.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1342,10 +1342,9 @@ static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, AAResults *AA,
13421342

13431343
// If Scalable Location Size has non-zero offset,
13441344
// Width + Offset does not work at the moment
1345-
if ((WidthA.isScalable() && (OffsetA > 0)) ||
1346-
(WidthB.isScalable() && (OffsetB > 0))) {
1345+
if ((WidthA.isScalable() && OffsetA > 0) ||
1346+
(WidthB.isScalable() && OffsetB > 0))
13471347
return true;
1348-
}
13491348

13501349
int64_t OverlapA = KnownWidthA
13511350
? WidthA.getKnownMinValue() + OffsetA - MinOffset

‎llvm/lib/CodeGen/MachineOperand.cpp

Lines changed: 7 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1098,20 +1098,18 @@ MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
10981098
s == ~UINT64_C(0) ? LLT() : LLT::scalar(8 * s), a,
10991099
AAInfo, Ranges, SSID, Ordering, FailureOrdering) {}
11001100

1101-
MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
1102-
TypeSize ts, Align a,
1101+
MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags F,
1102+
TypeSize TS, Align BaseAlignment,
11031103
const AAMDNodes &AAInfo,
11041104
const MDNode *Ranges, SyncScope::ID SSID,
11051105
AtomicOrdering Ordering,
11061106
AtomicOrdering FailureOrdering)
11071107
: MachineMemOperand(
1108-
ptrinfo, f,
1109-
ts.getKnownMinValue() == ~UINT64_C(0)
1110-
? LLT()
1111-
: ts.isScalable()
1112-
? LLT::scalable_vector(1, 8 * ts.getKnownMinValue())
1113-
: LLT::scalar(8 * ts.getKnownMinValue()),
1114-
a, AAInfo, Ranges, SSID, Ordering, FailureOrdering) {}
1108+
ptrinfo, F,
1109+
TS.getKnownMinValue() == ~UINT64_C(0) ? LLT()
1110+
: TS.isScalable() ? LLT::scalable_vector(1, 8 * TS.getKnownMinValue())
1111+
: LLT::scalar(8 * TS.getKnownMinValue()),
1112+
BaseAlignment, AAInfo, Ranges, SSID, Ordering, FailureOrdering) {}
11151113

11161114
void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
11171115
// The Value and Offset may differ due to CSE. But the flags and size

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 21 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -27848,7 +27848,7 @@ bool DAGCombiner::mayAlias(SDNode *Op0, SDNode *Op1) const {
2784827848
LN->getOperand(1),
2784927849
(LN->hasOffset()) ? LN->getOffset() : 0,
2785027850
(LN->hasOffset())
27851-
? std::optional<TypeSize>(TypeSize::getFixed(LN->getSize()))
27851+
? std::optional<TypeSize>(TypeSize::Fixed(LN->getSize()))
2785227852
: std::optional<TypeSize>(),
2785327853
(MachineMemOperand *)nullptr};
2785427854
// Default.
@@ -27881,20 +27881,15 @@ bool DAGCombiner::mayAlias(SDNode *Op0, SDNode *Op1) const {
2788127881
return false;
2788227882
}
2788327883

27884-
// if NumBytes is scalable and offset is not 0, conservatively return may
27884+
// If NumBytes is scalable and offset is not 0, conservatively return may
2788527885
// alias
27886-
if ((MUC0.NumBytes && MUC0.NumBytes.value().isScalable() &&
27887-
(MUC0.Offset != 0)) ||
27888-
(MUC1.NumBytes && MUC1.NumBytes.value().isScalable() &&
27889-
(MUC1.Offset != 0)))
27886+
if ((MUC0.NumBytes && MUC0.NumBytes->isScalable() && MUC0.Offset != 0) ||
27887+
(MUC1.NumBytes && MUC1.NumBytes->isScalable() && MUC1.Offset != 0))
2789027888
return true;
2789127889
// Try to prove that there is aliasing, or that there is no aliasing. Either
2789227890
// way, we can return now. If nothing can be proved, proceed with more tests.
27893-
const bool BothNotScalable = !(MUC0.NumBytes.value().isScalable() ||
27894-
MUC1.NumBytes.value().isScalable());
2789527891
bool IsAlias;
27896-
if (BothNotScalable &&
27897-
BaseIndexOffset::computeAliasing(Op0, MUC0.NumBytes, Op1, MUC1.NumBytes,
27892+
if (BaseIndexOffset::computeAliasing(Op0, MUC0.NumBytes, Op1, MUC1.NumBytes,
2789827893
DAG, IsAlias))
2789927894
return IsAlias;
2790027895

@@ -27922,20 +27917,18 @@ bool DAGCombiner::mayAlias(SDNode *Op0, SDNode *Op1) const {
2792227917
auto &Size0 = MUC0.NumBytes;
2792327918
auto &Size1 = MUC1.NumBytes;
2792427919

27925-
if (BothNotScalable) {
27926-
if (OrigAlignment0 == OrigAlignment1 && SrcValOffset0 != SrcValOffset1 &&
27927-
Size0.has_value() && Size1.has_value() && *Size0 == *Size1 &&
27928-
OrigAlignment0 > *Size0 && SrcValOffset0 % *Size0 == 0 &&
27929-
SrcValOffset1 % *Size1 == 0) {
27930-
int64_t OffAlign0 = SrcValOffset0 % OrigAlignment0.value();
27931-
int64_t OffAlign1 = SrcValOffset1 % OrigAlignment1.value();
27932-
27933-
// There is no overlap between these relatively aligned accesses of
27934-
// similar size. Return no alias.
27935-
if ((OffAlign0 + *Size0) <= OffAlign1 ||
27936-
(OffAlign1 + *Size1) <= OffAlign0)
27937-
return false;
27938-
}
27920+
if (OrigAlignment0 == OrigAlignment1 && SrcValOffset0 != SrcValOffset1 &&
27921+
Size0.has_value() && Size1.has_value() && !Size0->isScalable() &&
27922+
!Size1->isScalable() && *Size0 == *Size1 && OrigAlignment0 > *Size0 &&
27923+
SrcValOffset0 % *Size0 == 0 && SrcValOffset1 % *Size1 == 0) {
27924+
int64_t OffAlign0 = SrcValOffset0 % OrigAlignment0.value();
27925+
int64_t OffAlign1 = SrcValOffset1 % OrigAlignment1.value();
27926+
27927+
// There is no overlap between these relatively aligned accesses of
27928+
// similar size. Return no alias.
27929+
if ((OffAlign0 + static_cast<int64_t>(*Size0)) <= OffAlign1 ||
27930+
(OffAlign1 + static_cast<int64_t>(*Size1)) <= OffAlign0)
27931+
return false;
2793927932
}
2794027933

2794127934
bool UseAA = CombinerGlobalAA.getNumOccurrences() > 0
@@ -27951,14 +27944,12 @@ bool DAGCombiner::mayAlias(SDNode *Op0, SDNode *Op1) const {
2795127944
Size1) {
2795227945
// Use alias analysis information.
2795327946
int64_t MinOffset = std::min(SrcValOffset0, SrcValOffset1);
27954-
int64_t Overlap0 =
27955-
Size0.value().getKnownMinValue() + SrcValOffset0 - MinOffset;
27956-
int64_t Overlap1 =
27957-
Size1.value().getKnownMinValue() + SrcValOffset1 - MinOffset;
27958-
LocationSize Loc0 = Size0.value().isScalable()
27947+
int64_t Overlap0 = Size0->getKnownMinValue() + SrcValOffset0 - MinOffset;
27948+
int64_t Overlap1 = Size1->getKnownMinValue() + SrcValOffset1 - MinOffset;
27949+
LocationSize Loc0 = Size0->isScalable()
2795927950
? LocationSize::precise(Size0.value())
2796027951
: LocationSize::precise(Overlap0);
27961-
LocationSize Loc1 = Size1.value().isScalable()
27952+
LocationSize Loc1 = Size1->isScalable()
2796227953
? LocationSize::precise(Size1.value())
2796327954
: LocationSize::precise(Overlap1);
2796427955
if (AA->isNoAlias(

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -11779,9 +11779,9 @@ MemSDNode::MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl,
1177911779
// We check here that the size of the memory operand fits within the size of
1178011780
// the MMO. This is because the MMO might indicate only a possible address
1178111781
// range instead of specifying the affected memory addresses precisely.
11782-
if (MMO->getType().isValid())
11783-
assert(TypeSize::isKnownLE(memvt.getStoreSize(), MMO->getSize()) &&
11784-
"Size mismatch!");
11782+
assert((!MMO->getType().isValid() ||
11783+
TypeSize::isKnownLE(memvt.getStoreSize(), MMO->getSize())) &&
11784+
"Size mismatch!");
1178511785
}
1178611786

1178711787
/// Profile - Gather unique data for the node.

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp

Lines changed: 8 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -85,11 +85,10 @@ bool BaseIndexOffset::equalBaseIndex(const BaseIndexOffset &Other,
8585
}
8686

8787
bool BaseIndexOffset::computeAliasing(const SDNode *Op0,
88-
const std::optional<int64_t> NumBytes0,
88+
const std::optional<TypeSize> NumBytes0,
8989
const SDNode *Op1,
90-
const std::optional<int64_t> NumBytes1,
90+
const std::optional<TypeSize> NumBytes1,
9191
const SelectionDAG &DAG, bool &IsAlias) {
92-
9392
BaseIndexOffset BasePtr0 = match(Op0, DAG);
9493
BaseIndexOffset BasePtr1 = match(Op1, DAG);
9594

@@ -103,20 +102,20 @@ bool BaseIndexOffset::computeAliasing(const SDNode *Op0,
103102
// vector objects on the stack.
104103
// BasePtr1 is PtrDiff away from BasePtr0. They alias if none of the
105104
// following situations arise:
106-
if (PtrDiff >= 0 &&
107-
*NumBytes0 != static_cast<int64_t>(MemoryLocation::UnknownSize)) {
105+
if (PtrDiff >= 0 && !NumBytes0->isScalable() &&
106+
NumBytes0->getFixedValue() != MemoryLocation::UnknownSize) {
108107
// [----BasePtr0----]
109108
// [---BasePtr1--]
110109
// ========PtrDiff========>
111-
IsAlias = !(*NumBytes0 <= PtrDiff);
110+
IsAlias = !((int64_t)NumBytes0->getFixedValue() <= PtrDiff);
112111
return true;
113112
}
114-
if (PtrDiff < 0 &&
115-
*NumBytes1 != static_cast<int64_t>(MemoryLocation::UnknownSize)) {
113+
if (PtrDiff < 0 && !NumBytes1->isScalable() &&
114+
NumBytes1->getFixedValue() != MemoryLocation::UnknownSize) {
116115
// [----BasePtr0----]
117116
// [---BasePtr1--]
118117
// =====(-PtrDiff)====>
119-
IsAlias = !((PtrDiff + *NumBytes1) <= 0);
118+
IsAlias = !((PtrDiff + (int64_t)NumBytes1->getFixedValue()) <= 0);
120119
return true;
121120
}
122121
return false;

‎llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -172,14 +172,16 @@ bool HexagonStoreWidening::instrAliased(InstrGroup &Stores,
172172
if (!MMO.getValue())
173173
return true;
174174

175-
MemoryLocation L(MMO.getValue(), MMO.getSize(), MMO.getAAInfo());
175+
MemoryLocation L(MMO.getValue(), MMO.getSize().getFixedValue(),
176+
MMO.getAAInfo());
176177

177178
for (auto *SI : Stores) {
178179
const MachineMemOperand &SMO = getStoreTarget(SI);
179180
if (!SMO.getValue())
180181
return true;
181182

182-
MemoryLocation SL(SMO.getValue(), SMO.getSize(), SMO.getAAInfo());
183+
MemoryLocation SL(SMO.getValue(), SMO.getSize().getFixedValue(),
184+
SMO.getAAInfo());
183185
if (!AA->isNoAlias(L, SL))
184186
return true;
185187
}

0 commit comments

Comments
 (0)