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[CodeGen] Remove target SubRegLiveness flags (#95437)
This removes the uses of target flags to disable subreg liveness, relying on the `-enable-subreg-liveness` flag instead. The `-enable-subreg-liveness` flag has been changed to take precedence over the subtarget if set, and one use of `Subtarget->enableSubRegLiveness()` has been changed to `MRI->subRegLivenessEnabled()` to make sure the option properly applies.
1 parent d712ae4 commit 706e197

23 files changed

+38
-61
lines changed

‎llvm/lib/CodeGen/InitUndef.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -238,7 +238,7 @@ bool InitUndef::processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB,
238238
}
239239

240240
if (isEarlyClobberMI(MI)) {
241-
if (ST->enableSubRegLiveness())
241+
if (MRI->subRegLivenessEnabled())
242242
Changed |= handleSubReg(MF, MI, DLD);
243243
Changed |= handleReg(&MI);
244244
}

‎llvm/lib/CodeGen/MachineRegisterInfo.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -41,8 +41,10 @@ static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden,
4141
void MachineRegisterInfo::Delegate::anchor() {}
4242

4343
MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF)
44-
: MF(MF), TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() &&
45-
EnableSubRegLiveness) {
44+
: MF(MF),
45+
TracksSubRegLiveness(EnableSubRegLiveness.getNumOccurrences()
46+
? EnableSubRegLiveness
47+
: MF->getSubtarget().enableSubRegLiveness()) {
4648
unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
4749
VRegInfo.reserve(256);
4850
RegAllocHints.reserve(256);

‎llvm/lib/Target/ARM/ARMSubtarget.cpp

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -68,9 +68,6 @@ static cl::opt<bool>
6868
ForceFastISel("arm-force-fast-isel",
6969
cl::init(false), cl::Hidden);
7070

71-
static cl::opt<bool> EnableSubRegLiveness("arm-enable-subreg-liveness",
72-
cl::init(false), cl::Hidden);
73-
7471
/// initializeSubtargetDependencies - Initializes using a CPU and feature string
7572
/// so that we can use initializer lists for subtarget initialization.
7673
ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
@@ -385,8 +382,6 @@ bool ARMSubtarget::enableMachineScheduler() const {
385382
}
386383

387384
bool ARMSubtarget::enableSubRegLiveness() const {
388-
if (EnableSubRegLiveness.getNumOccurrences())
389-
return EnableSubRegLiveness;
390385
// Enable SubRegLiveness for MVE to better optimize s subregs for mqpr regs
391386
// and q subregs for qqqqpr regs.
392387
return hasMVEIntegerOps();

‎llvm/lib/Target/Hexagon/HexagonSubtarget.cpp

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -55,10 +55,6 @@ static cl::opt<bool>
5555
DisableHexagonMISched("disable-hexagon-misched", cl::Hidden,
5656
cl::desc("Disable Hexagon MI Scheduling"));
5757

58-
static cl::opt<bool> EnableSubregLiveness(
59-
"hexagon-subreg-liveness", cl::Hidden, cl::init(true),
60-
cl::desc("Enable subregister liveness tracking for Hexagon"));
61-
6258
static cl::opt<bool> OverrideLongCalls(
6359
"hexagon-long-calls", cl::Hidden,
6460
cl::desc("If present, forces/disables the use of long calls"));
@@ -726,9 +722,7 @@ unsigned HexagonSubtarget::getL1PrefetchDistance() const {
726722
return 32;
727723
}
728724

729-
bool HexagonSubtarget::enableSubRegLiveness() const {
730-
return EnableSubregLiveness;
731-
}
725+
bool HexagonSubtarget::enableSubRegLiveness() const { return true; }
732726

733727
Intrinsic::ID HexagonSubtarget::getIntrinsicId(unsigned Opc) const {
734728
struct Scalar {

‎llvm/lib/Target/PowerPC/PPCSubtarget.cpp

Lines changed: 1 addition & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -37,11 +37,6 @@ using namespace llvm;
3737
#define GET_SUBTARGETINFO_CTOR
3838
#include "PPCGenSubtargetInfo.inc"
3939

40-
static cl::opt<bool>
41-
UseSubRegLiveness("ppc-track-subreg-liveness",
42-
cl::desc("Enable subregister liveness tracking for PPC"),
43-
cl::init(true), cl::Hidden);
44-
4540
static cl::opt<bool>
4641
EnableMachinePipeliner("ppc-enable-pipeliner",
4742
cl::desc("Enable Machine Pipeliner for PPC"),
@@ -186,9 +181,7 @@ bool PPCSubtarget::useAA() const {
186181
return true;
187182
}
188183

189-
bool PPCSubtarget::enableSubRegLiveness() const {
190-
return UseSubRegLiveness;
191-
}
184+
bool PPCSubtarget::enableSubRegLiveness() const { return true; }
192185

193186
bool PPCSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const {
194187
if (isAIXABI()) {

‎llvm/lib/Target/RISCV/RISCVSubtarget.cpp

Lines changed: 1 addition & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -39,9 +39,6 @@ namespace llvm::RISCVTuneInfoTable {
3939
#include "RISCVGenSearchableTables.inc"
4040
} // namespace llvm::RISCVTuneInfoTable
4141

42-
static cl::opt<bool> EnableSubRegLiveness("riscv-enable-subreg-liveness",
43-
cl::init(true), cl::Hidden);
44-
4542
static cl::opt<unsigned> RVVVectorLMULMax(
4643
"riscv-v-fixed-length-vector-lmul-max",
4744
cl::desc("The maximum LMUL value to use for fixed length vectors. "
@@ -183,11 +180,7 @@ bool RISCVSubtarget::useRVVForFixedLengthVectors() const {
183180
return hasVInstructions() && getMinRVVVectorSizeInBits() != 0;
184181
}
185182

186-
bool RISCVSubtarget::enableSubRegLiveness() const {
187-
// FIXME: Enable subregister liveness by default for RVV to better handle
188-
// LMUL>1 and segment load/store.
189-
return EnableSubRegLiveness;
190-
}
183+
bool RISCVSubtarget::enableSubRegLiveness() const { return true; }
191184

192185
void RISCVSubtarget::getPostRAMutations(
193186
std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {

‎llvm/test/CodeGen/ARM/regcoal-invalid-subrange-update.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc %s -start-before register-coalescer -mtriple=arm-apple-ios -stop-after machine-scheduler -o - -arm-enable-subreg-liveness -verify-machineinstrs | FileCheck %s
2+
# RUN: llc %s -start-before register-coalescer -mtriple=arm-apple-ios -stop-after machine-scheduler -o - -enable-subreg-liveness -verify-machineinstrs | FileCheck %s
33

44
# Check that when we merge live-ranges that imply offseting
55
# the definition of a subregister by some other subreg index,

‎llvm/test/CodeGen/Hexagon/bit-gen-rseq.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
; RUN: llc -march=hexagon -disable-hsdr -hexagon-subreg-liveness < %s | FileCheck %s
1+
; RUN: llc -march=hexagon -disable-hsdr -enable-subreg-liveness < %s | FileCheck %s
22
; Check that we don't generate any bitwise operations.
33

44
; CHECK-NOT: = or(

‎llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
# RUN: llc -march=hexagon -hexagon-subreg-liveness -start-after machine-scheduler -stop-after stack-slot-coloring -o - %s | FileCheck %s
1+
# RUN: llc -march=hexagon -enable-subreg-liveness -start-after machine-scheduler -stop-after stack-slot-coloring -o - %s | FileCheck %s
22

33
--- |
44
target triple = "hexagon"

‎llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
# Using a trick to run register-coalescer twice, that way
22
# liveintervals should be preserved while running the machine verifier.
33
#
4-
# RUN: not --crash llc -o - %s -march=hexagon -hexagon-subreg-liveness=false -run-pass register-coalescer -verify-machineinstrs -run-pass register-coalescer 2>&1 | FileCheck -check-prefix=CHECK-NOSUB %s
5-
# RUN: not --crash llc -o - %s -march=hexagon -hexagon-subreg-liveness=true -run-pass register-coalescer -verify-machineinstrs -run-pass register-coalescer 2>&1 | FileCheck -check-prefix=CHECK-SUB %s
4+
# RUN: not --crash llc -o - %s -march=hexagon -enable-subreg-liveness=false -run-pass register-coalescer -verify-machineinstrs -run-pass register-coalescer 2>&1 | FileCheck -check-prefix=CHECK-NOSUB %s
5+
# RUN: not --crash llc -o - %s -march=hexagon -enable-subreg-liveness=true -run-pass register-coalescer -verify-machineinstrs -run-pass register-coalescer 2>&1 | FileCheck -check-prefix=CHECK-SUB %s
66

77
---
88
name: test_pass

‎llvm/test/CodeGen/PowerPC/atomics-i128-ldst.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,21 +1,21 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
3-
; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-track-subreg-liveness \
3+
; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -enable-subreg-liveness \
44
; RUN: < %s | FileCheck --check-prefix=P8 %s
55
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown -mcpu=pwr7 \
66
; RUN: -ppc-asm-full-reg-names \
7-
; RUN: -ppc-track-subreg-liveness < %s | FileCheck --check-prefix=PWR7 %s
7+
; RUN: -enable-subreg-liveness < %s | FileCheck --check-prefix=PWR7 %s
88
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 \
9-
; RUN: -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
9+
; RUN: -ppc-asm-full-reg-names -enable-subreg-liveness < %s | FileCheck \
1010
; RUN: --check-prefix=LE-PWR8 %s
1111
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-freebsd -mcpu=pwr8 \
12-
; RUN: -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
12+
; RUN: -ppc-asm-full-reg-names -enable-subreg-liveness < %s | FileCheck \
1313
; RUN: --check-prefix=LE-PWR8 %s
1414
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr8 \
15-
; RUN: -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
15+
; RUN: -ppc-asm-full-reg-names -enable-subreg-liveness < %s | FileCheck \
1616
; RUN: --check-prefix=AIX64-PWR8 %s
1717
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-unknown -mcpu=pwr8 \
18-
; RUN: -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s \
18+
; RUN: -ppc-asm-full-reg-names -enable-subreg-liveness < %s \
1919
; RUN: | FileCheck --check-prefix=PPC-PWR8 %s
2020

2121
define dso_local i128 @lq_unordered(ptr %src) {

‎llvm/test/CodeGen/PowerPC/atomics-i128.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,25 +1,25 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown -mcpu=pwr8 \
33
; RUN: -ppc-asm-full-reg-names \
4-
; RUN: -ppc-track-subreg-liveness < %s | FileCheck %s
4+
; RUN: -enable-subreg-liveness < %s | FileCheck %s
55
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown -mcpu=pwr7 \
66
; RUN: -ppc-asm-full-reg-names \
7-
; RUN: -ppc-track-subreg-liveness < %s | FileCheck --check-prefix=PWR7 %s
7+
; RUN: -enable-subreg-liveness < %s | FileCheck --check-prefix=PWR7 %s
88
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 \
9-
; RUN: -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
9+
; RUN: -ppc-asm-full-reg-names -enable-subreg-liveness < %s | FileCheck \
1010
; RUN: --check-prefix=LE-PWR8 %s
1111
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-freebsd -mcpu=pwr8 \
12-
; RUN: -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
12+
; RUN: -ppc-asm-full-reg-names -enable-subreg-liveness < %s | FileCheck \
1313
; RUN: --check-prefix=LE-PWR8 %s
1414
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr8 \
15-
; RUN: -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
15+
; RUN: -ppc-asm-full-reg-names -enable-subreg-liveness < %s | FileCheck \
1616
; RUN: --check-prefix=AIX64-PWR8 %s
1717

1818
; On 32-bit PPC platform, 16-byte lock free atomic instructions are not available,
1919
; it's expected not to generate inlined lock-free code on such platforms, even arch level
2020
; is pwr8+ and `-ppc-quadword-atomics` is on.
2121
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-unknown -mcpu=pwr8 \
22-
; RUN: -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s \
22+
; RUN: -ppc-asm-full-reg-names -enable-subreg-liveness < %s \
2323
; RUN: | FileCheck --check-prefix=PPC-PWR8 %s
2424

2525

‎llvm/test/CodeGen/PowerPC/mma-outer-product.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3-
; RUN: -mcpu=pwr10 -ppc-track-subreg-liveness -ppc-asm-full-reg-names \
3+
; RUN: -mcpu=pwr10 -enable-subreg-liveness -ppc-asm-full-reg-names \
44
; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
55
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
6-
; RUN: -mcpu=pwr10 -ppc-track-subreg-liveness -ppc-asm-full-reg-names \
6+
; RUN: -mcpu=pwr10 -enable-subreg-liveness -ppc-asm-full-reg-names \
77
; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
88

99
declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)

‎llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
; RUN: | FileCheck %s
55
; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu \
66
; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
7-
; RUN: -ppc-track-subreg-liveness < %s | FileCheck %s --check-prefix=TRACKLIVE
7+
; RUN: -enable-subreg-liveness < %s | FileCheck %s --check-prefix=TRACKLIVE
88

99
%0 = type <{ double }>
1010
%1 = type <{ double }>

‎llvm/test/CodeGen/PowerPC/subreg-killed.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
# RUN: llc -mcpu=pwr10 -O3 -ppc-track-subreg-liveness -verify-machineinstrs \
1+
# RUN: llc -mcpu=pwr10 -O3 -enable-subreg-liveness -verify-machineinstrs \
22
# RUN: -mtriple=powerpc64le-unknown-linux-gnu -run-pass=greedy,virtregrewriter \
33
# RUN: -o - %s | FileCheck %s
44

‎llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -O2 -mtriple riscv64 -mattr=+v,+m,+zbb -riscv-enable-subreg-liveness \
2+
; RUN: llc -O2 -mtriple riscv64 -mattr=+v,+m,+zbb -enable-subreg-liveness \
33
; RUN: -verify-machineinstrs < %s \
44
; RUN: | FileCheck %s
55

‎llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=riscv64 -mattr=+f,+m,+zfh,+zvfh \
3-
; RUN: -riscv-enable-subreg-liveness=false < %s | FileCheck %s
3+
; RUN: -enable-subreg-liveness=false < %s | FileCheck %s
44
; RUN: llc -mtriple=riscv64 -mattr=+f,+m,+zfh,+zvfh < %s \
5-
; RUN: -riscv-enable-subreg-liveness=true| FileCheck %s --check-prefix=SUBREGLIVENESS
5+
; RUN: -enable-subreg-liveness=true| FileCheck %s --check-prefix=SUBREGLIVENESS
66

77
; This testcase failed to compile after
88
; c46aab01c002b7a04135b8b7f1f52d8c9ae23a58, which was reverted.

‎llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc %s -mtriple=riscv64 -mattr=+v -riscv-enable-subreg-liveness -run-pass=init-undef -o - | FileCheck %s
2+
# RUN: llc %s -mtriple=riscv64 -mattr=+v -enable-subreg-liveness -run-pass=init-undef -o - | FileCheck %s
33

44
...
55
---

‎llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple riscv64 -mattr=+v -riscv-enable-subreg-liveness < %s | FileCheck %s
2+
; RUN: llc -mtriple riscv64 -mattr=+v -enable-subreg-liveness < %s | FileCheck %s
33

44
define <vscale x 2 x float> @vrgather_all_undef(ptr %p) {
55
; CHECK-LABEL: vrgather_all_undef:

‎llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc -mtriple=riscv32 -mattr=+v -riscv-enable-subreg-liveness -run-pass init-undef -run-pass machineverifier %s -o - | FileCheck %s
2+
# RUN: llc -mtriple=riscv32 -mattr=+v -enable-subreg-liveness -run-pass init-undef -run-pass machineverifier %s -o - | FileCheck %s
33

44
--- |
55
source_filename = "<stdin>"

‎llvm/test/CodeGen/RISCV/rvv/vrgatherei16-subreg-liveness.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefix NOSUBREG
3-
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s -riscv-enable-subreg-liveness=true | FileCheck %s --check-prefix SUBREG
3+
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s -enable-subreg-liveness=true | FileCheck %s --check-prefix SUBREG
44

55
; This test checks that vrgatherei16 instructions are correctly
66
; register-allocated. The LMUL=1 destination register groups may not overlap

‎llvm/test/CodeGen/Thumb2/LowOverheadLoops/spillingmove.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc -mtriple=thumbv8.1m.main-none-unknown-eabi -mattr=+mve -run-pass=arm-low-overhead-loops -arm-enable-subreg-liveness %s -o - --verify-machineinstrs | FileCheck %s
2+
# RUN: llc -mtriple=thumbv8.1m.main-none-unknown-eabi -mattr=+mve -run-pass=arm-low-overhead-loops -enable-subreg-liveness %s -o - --verify-machineinstrs | FileCheck %s
33

44
--- |
55
%struct.arm_2d_size_t = type { i16, i16 }

‎llvm/test/CodeGen/Thumb2/LowOverheadLoops/subreg-liveness.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops -arm-enable-subreg-liveness %s -o - --verify-machineinstrs | FileCheck %s
2+
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops -enable-subreg-liveness %s -o - --verify-machineinstrs | FileCheck %s
33

44
--- |
55
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"

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