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[RISCV] Prefer RegList over Rlist in assembler. NFC
This makes it more obvious what the R means. I've kept rlist in place that refer to the encoding.
1 parent f9193f3 commit 70a1445

8 files changed

+61
-61
lines changed

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Lines changed: 30 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -215,10 +215,10 @@ class RISCVAsmParser : public MCTargetAsmParser {
215215
ParseStatus parseGPRPair(OperandVector &Operands, bool IsRV64Inst);
216216
ParseStatus parseFRMArg(OperandVector &Operands);
217217
ParseStatus parseFenceArg(OperandVector &Operands);
218-
ParseStatus parseReglist(OperandVector &Operands) {
218+
ParseStatus parseRegList(OperandVector &Operands) {
219219
return parseRegListCommon(Operands, /*MustIncludeS0=*/false);
220220
}
221-
ParseStatus parseReglistS0(OperandVector &Operands) {
221+
ParseStatus parseRegListS0(OperandVector &Operands) {
222222
return parseRegListCommon(Operands, /*MustIncludeS0=*/true);
223223
}
224224
ParseStatus parseRegListCommon(OperandVector &Operands, bool MustIncludeS0);
@@ -349,7 +349,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
349349
VType,
350350
FRM,
351351
Fence,
352-
Rlist,
352+
RegList,
353353
Spimm,
354354
RegReg,
355355
} Kind;
@@ -388,8 +388,8 @@ struct RISCVOperand final : public MCParsedAsmOperand {
388388
unsigned Val;
389389
};
390390

391-
struct RlistOp {
392-
unsigned Val;
391+
struct RegListOp {
392+
unsigned Encoding;
393393
};
394394

395395
struct SpimmOp {
@@ -411,7 +411,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
411411
VTypeOp VType;
412412
FRMOp FRM;
413413
FenceOp Fence;
414-
RlistOp Rlist;
414+
RegListOp RegList;
415415
SpimmOp Spimm;
416416
RegRegOp RegReg;
417417
};
@@ -448,8 +448,8 @@ struct RISCVOperand final : public MCParsedAsmOperand {
448448
case KindTy::Fence:
449449
Fence = o.Fence;
450450
break;
451-
case KindTy::Rlist:
452-
Rlist = o.Rlist;
451+
case KindTy::RegList:
452+
RegList = o.RegList;
453453
break;
454454
case KindTy::Spimm:
455455
Spimm = o.Spimm;
@@ -482,9 +482,9 @@ struct RISCVOperand final : public MCParsedAsmOperand {
482482
bool isMem() const override { return false; }
483483
bool isSystemRegister() const { return Kind == KindTy::SystemRegister; }
484484
bool isRegReg() const { return Kind == KindTy::RegReg; }
485-
bool isRlist() const { return Kind == KindTy::Rlist; }
486-
bool isRlistS0() const {
487-
return Kind == KindTy::Rlist && Rlist.Val != RISCVZC::RA;
485+
bool isRegList() const { return Kind == KindTy::RegList; }
486+
bool isRegListS0() const {
487+
return Kind == KindTy::RegList && RegList.Encoding != RISCVZC::RA;
488488
}
489489
bool isSpimm() const { return Kind == KindTy::Spimm; }
490490

@@ -1009,9 +1009,9 @@ struct RISCVOperand final : public MCParsedAsmOperand {
10091009
OS << getFence();
10101010
OS << '>';
10111011
break;
1012-
case KindTy::Rlist:
1013-
OS << "<rlist: ";
1014-
RISCVZC::printRlist(Rlist.Val, OS);
1012+
case KindTy::RegList:
1013+
OS << "<reglist: ";
1014+
RISCVZC::printRegList(RegList.Encoding, OS);
10151015
OS << '>';
10161016
break;
10171017
case KindTy::Spimm:
@@ -1098,10 +1098,10 @@ struct RISCVOperand final : public MCParsedAsmOperand {
10981098
return Op;
10991099
}
11001100

1101-
static std::unique_ptr<RISCVOperand> createRlist(unsigned RlistEncode,
1101+
static std::unique_ptr<RISCVOperand> createRegList(unsigned RlistEncode,
11021102
SMLoc S) {
1103-
auto Op = std::make_unique<RISCVOperand>(KindTy::Rlist);
1104-
Op->Rlist.Val = RlistEncode;
1103+
auto Op = std::make_unique<RISCVOperand>(KindTy::RegList);
1104+
Op->RegList.Encoding = RlistEncode;
11051105
Op->StartLoc = S;
11061106
return Op;
11071107
}
@@ -1183,9 +1183,9 @@ struct RISCVOperand final : public MCParsedAsmOperand {
11831183
Inst.addOperand(MCOperand::createImm(Imm));
11841184
}
11851185

1186-
void addRlistOperands(MCInst &Inst, unsigned N) const {
1186+
void addRegListOperands(MCInst &Inst, unsigned N) const {
11871187
assert(N == 1 && "Invalid number of operands!");
1188-
Inst.addOperand(MCOperand::createImm(Rlist.Val));
1188+
Inst.addOperand(MCOperand::createImm(RegList.Encoding));
11891189
}
11901190

11911191
void addRegRegOperands(MCInst &Inst, unsigned N) const {
@@ -2569,13 +2569,13 @@ ParseStatus RISCVAsmParser::parseRegReg(OperandVector &Operands) {
25692569

25702570
ParseStatus RISCVAsmParser::parseRegListCommon(OperandVector &Operands,
25712571
bool MustIncludeS0) {
2572-
// Rlist: {ra [, s0[-sN]]}
2573-
// XRlist: {x1 [, x8[-x9][, x18[-xN]]]}
2572+
// RegList: {ra [, s0[-sN]]}
2573+
// XRegList: {x1 [, x8[-x9][, x18[-xN]]]}
25742574

25752575
// When MustIncludeS0 = true (not the default) (used for `qc.cm.pushfp`) which
25762576
// must include `fp`/`s0` in the list:
2577-
// Rlist: {ra, s0[-sN]}
2578-
// XRlist: {x1, x8[-x9][, x18[-xN]]}
2577+
// RegList: {ra, s0[-sN]}
2578+
// XRegList: {x1, x8[-x9][, x18[-xN]]}
25792579

25802580
if (getTok().isNot(AsmToken::LCurly))
25812581
return ParseStatus::NoMatch;
@@ -2656,13 +2656,13 @@ ParseStatus RISCVAsmParser::parseRegListCommon(OperandVector &Operands,
26562656
return Error(S, "invalid register list, {ra, s0-s10} or {x1, x8-x9, "
26572657
"x18-x26} is not supported");
26582658

2659-
auto Encode = RISCVZC::encodeRlist(RegEnd, IsRVE);
2659+
auto Encode = RISCVZC::encodeRegList(RegEnd, IsRVE);
26602660
assert(Encode != RISCVZC::INVALID_RLIST);
26612661

26622662
if (MustIncludeS0 && Encode == RISCVZC::RA)
26632663
return Error(S, "register list must include 's0' or 'x8'");
26642664

2665-
Operands.push_back(RISCVOperand::createRlist(Encode, S));
2665+
Operands.push_back(RISCVOperand::createRegList(Encode, S));
26662666

26672667
return ParseStatus::Success;
26682668
}
@@ -2677,14 +2677,14 @@ ParseStatus RISCVAsmParser::parseZcmpStackAdj(OperandVector &Operands,
26772677

26782678
int64_t StackAdjustment = getTok().getIntVal();
26792679

2680-
auto *RListOp = static_cast<RISCVOperand *>(Operands.back().get());
2681-
if (!RListOp->isRlist())
2680+
auto *RegListOp = static_cast<RISCVOperand *>(Operands.back().get());
2681+
if (!RegListOp->isRegList())
26822682
return ParseStatus::NoMatch;
26832683

2684-
unsigned RlistVal = RListOp->Rlist.Val;
2684+
unsigned RlistEncode = RegListOp->RegList.Encoding;
26852685

2686-
assert(RlistVal != RISCVZC::INVALID_RLIST);
2687-
unsigned StackAdjBase = RISCVZC::getStackAdjBase(RlistVal, isRV64());
2686+
assert(RlistEncode != RISCVZC::INVALID_RLIST);
2687+
unsigned StackAdjBase = RISCVZC::getStackAdjBase(RlistEncode, isRV64());
26882688
if (Negative != ExpectNegative || StackAdjustment % 16 != 0 ||
26892689
StackAdjustment < StackAdjBase || (StackAdjustment - StackAdjBase) > 48) {
26902690
int64_t Lower = StackAdjBase;

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -240,14 +240,14 @@ float RISCVLoadFPImm::getFPImm(unsigned Imm) {
240240
return bit_cast<float>(I);
241241
}
242242

243-
void RISCVZC::printRlist(unsigned SlistEncode, raw_ostream &OS) {
243+
void RISCVZC::printRegList(unsigned RlistEncode, raw_ostream &OS) {
244244
OS << "{ra";
245-
if (SlistEncode > RISCVZC::RA) {
245+
if (RlistEncode > RISCVZC::RA) {
246246
OS << ", s0";
247-
if (SlistEncode == RISCVZC::RA_S0_S11)
247+
if (RlistEncode == RISCVZC::RA_S0_S11)
248248
OS << "-s11";
249-
else if (SlistEncode > RISCVZC::RA_S0 && SlistEncode <= RISCVZC::RA_S0_S11)
250-
OS << "-s" << (SlistEncode - RISCVZC::RA_S0);
249+
else if (RlistEncode > RISCVZC::RA_S0 && RlistEncode <= RISCVZC::RA_S0_S11)
250+
OS << "-s" << (RlistEncode - RISCVZC::RA_S0);
251251
}
252252
OS << "}";
253253
}

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -609,7 +609,7 @@ enum RLISTENCODE {
609609
INVALID_RLIST,
610610
};
611611

612-
inline unsigned encodeRlist(MCRegister EndReg, bool IsRVE = false) {
612+
inline unsigned encodeRegList(MCRegister EndReg, bool IsRVE = false) {
613613
assert((!IsRVE || EndReg <= RISCV::X9) && "Invalid Rlist for RV32E");
614614
switch (EndReg) {
615615
case RISCV::X1:
@@ -641,7 +641,7 @@ inline unsigned encodeRlist(MCRegister EndReg, bool IsRVE = false) {
641641
}
642642
}
643643

644-
inline static unsigned encodeRlistNumRegs(unsigned NumRegs) {
644+
inline static unsigned encodeRegListNumRegs(unsigned NumRegs) {
645645
assert(NumRegs > 0 && NumRegs < 14 && NumRegs != 12 &&
646646
"Unexpected number of registers");
647647
if (NumRegs == 13)
@@ -662,7 +662,7 @@ inline static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64) {
662662
return alignTo(NumRegs * RegSize, 16);
663663
}
664664

665-
void printRlist(unsigned SlistEncode, raw_ostream &OS);
665+
void printRegList(unsigned RlistEncode, raw_ostream &OS);
666666
} // namespace RISCVZC
667667

668668
namespace RISCVVInversePseudosTable {

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -222,8 +222,8 @@ void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
222222
// Print a Zcmp RList. If we are printing architectural register names rather
223223
// than ABI register names, we need to print "{x1, x8-x9, x18-x27}" for all
224224
// registers. Otherwise, we print "{ra, s0-s11}".
225-
void RISCVInstPrinter::printRlist(const MCInst *MI, unsigned OpNo,
226-
const MCSubtargetInfo &STI, raw_ostream &O) {
225+
void RISCVInstPrinter::printRegList(const MCInst *MI, unsigned OpNo,
226+
const MCSubtargetInfo &STI, raw_ostream &O) {
227227
unsigned Imm = MI->getOperand(OpNo).getImm();
228228
O << "{";
229229
printRegName(O, RISCV::X1);

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -50,8 +50,8 @@ class RISCVInstPrinter : public MCInstPrinter {
5050
raw_ostream &O);
5151
void printVMaskReg(const MCInst *MI, unsigned OpNo,
5252
const MCSubtargetInfo &STI, raw_ostream &O);
53-
void printRlist(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
54-
raw_ostream &O);
53+
void printRegList(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
54+
raw_ostream &O);
5555
void printStackAdj(const MCInst *MI, unsigned OpNo,
5656
const MCSubtargetInfo &STI, raw_ostream &O,
5757
bool Negate = false);

‎llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1989,7 +1989,7 @@ bool RISCVFrameLowering::spillCalleeSavedRegisters(
19891989
if (PushedRegNum > 0) {
19901990
// Use encoded number to represent registers to spill.
19911991
unsigned Opcode = getPushOpcode(RVFI->getPushPopKind(*MF), hasFP(*MF));
1992-
unsigned RegEnc = RISCVZC::encodeRlistNumRegs(PushedRegNum);
1992+
unsigned RegEnc = RISCVZC::encodeRegListNumRegs(PushedRegNum);
19931993
MachineInstrBuilder PushBuilder =
19941994
BuildMI(MBB, MI, DL, TII.get(Opcode))
19951995
.setMIFlag(MachineInstr::FrameSetup);
@@ -2151,7 +2151,7 @@ bool RISCVFrameLowering::restoreCalleeSavedRegisters(
21512151
unsigned PushedRegNum = RVFI->getRVPushRegs();
21522152
if (PushedRegNum > 0) {
21532153
unsigned Opcode = getPopOpcode(RVFI->getPushPopKind(*MF));
2154-
unsigned RegEnc = RISCVZC::encodeRlistNumRegs(PushedRegNum);
2154+
unsigned RegEnc = RISCVZC::encodeRegListNumRegs(PushedRegNum);
21552155
MachineInstrBuilder PopBuilder =
21562156
BuildMI(MBB, MI, DL, TII.get(Opcode))
21572157
.setMIFlag(MachineInstr::FrameDestroy);

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqccmp.td

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -25,17 +25,17 @@
2525
// Operand and SDNode transformation definitions.
2626
//===----------------------------------------------------------------------===//
2727

28-
def RlistS0AsmOperand : AsmOperandClass {
29-
let Name = "RlistS0";
30-
let ParserMethod = "parseReglistS0";
31-
let RenderMethod = "addRlistOperands";
32-
let DiagnosticType = "InvalidRlistS0";
28+
def RegListS0AsmOperand : AsmOperandClass {
29+
let Name = "RegListS0";
30+
let ParserMethod = "parseRegListS0";
31+
let RenderMethod = "addRegListOperands";
32+
let DiagnosticType = "InvalidRegListS0";
3333
let DiagnosticString = "operand must be {ra, s0[-sN]} or {x1, x8[-x9][, x18[-xN]]}";
3434
}
3535

36-
def rlist_s0 : RISCVOp<OtherVT> {
37-
let ParserMatchClass = RlistS0AsmOperand;
38-
let PrintMethod = "printRlist";
36+
def reglist_s0 : RISCVOp<OtherVT> {
37+
let ParserMatchClass = RegListS0AsmOperand;
38+
let PrintMethod = "printRegList";
3939
let DecoderMethod = "decodeXqccmpRlistS0";
4040
let EncoderMethod = "getRlistS0OpValue";
4141
let MCOperandPredicate = [{
@@ -59,7 +59,7 @@ def rlist_s0 : RISCVOp<OtherVT> {
5959

6060
class RVInstXqccmpCPPPFP<bits<5> funct5, string opcodestr,
6161
DAGOperand immtype = stackadj>
62-
: RVInst16<(outs), (ins rlist_s0:$rlist, immtype:$stackadj),
62+
: RVInst16<(outs), (ins reglist_s0:$rlist, immtype:$stackadj),
6363
opcodestr, "$rlist, $stackadj", [], InstFormatOther> {
6464
bits<4> rlist;
6565
bits<16> stackadj;

‎llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -35,10 +35,10 @@ def uimm8ge32 : RISCVOp {
3535
let OperandType = "OPERAND_UIMM8_GE32";
3636
}
3737

38-
def RlistAsmOperand : AsmOperandClass {
39-
let Name = "Rlist";
40-
let ParserMethod = "parseReglist";
41-
let DiagnosticType = "InvalidRlist";
38+
def RegListAsmOperand : AsmOperandClass {
39+
let Name = "RegList";
40+
let ParserMethod = "parseRegList";
41+
let DiagnosticType = "InvalidRegList";
4242
let DiagnosticString = "operand must be {ra [, s0[-sN]]} or {x1 [, x8[-x9][, x18[-xN]]]}";
4343
}
4444

@@ -58,9 +58,9 @@ def NegStackAdjAsmOperand : AsmOperandClass {
5858
let RenderMethod = "addSpimmOperands";
5959
}
6060

61-
def rlist : RISCVOp<OtherVT> {
62-
let ParserMatchClass = RlistAsmOperand;
63-
let PrintMethod = "printRlist";
61+
def reglist : RISCVOp<OtherVT> {
62+
let ParserMatchClass = RegListAsmOperand;
63+
let PrintMethod = "printRegList";
6464
let DecoderMethod = "decodeZcmpRlist";
6565
let EncoderMethod = "getRlistOpValue";
6666
let MCOperandPredicate = [{
@@ -155,7 +155,7 @@ class RVZcArith_r<bits<5> funct5, string OpcodeStr> :
155155

156156
class RVInstZcCPPP<bits<5> funct5, string opcodestr,
157157
DAGOperand immtype = stackadj>
158-
: RVInst16<(outs), (ins rlist:$rlist, immtype:$stackadj),
158+
: RVInst16<(outs), (ins reglist:$rlist, immtype:$stackadj),
159159
opcodestr, "$rlist, $stackadj", [], InstFormatOther> {
160160
bits<4> rlist;
161161
bits<16> stackadj;

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