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[AMDGPU][Attributor] Rework calculation of waves per eu
1 parent c3685eb commit 7167ec8

32 files changed

+383
-351
lines changed

clang/test/CodeGenOpenCL/builtins-amdgcn.cl

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -899,4 +899,5 @@ void test_set_fpenv(unsigned long env) {
899899

900900
// CHECK-DAG: [[$GRID_RANGE]] = !{i32 1, i32 0}
901901
// CHECK-DAG: [[$WS_RANGE]] = !{i16 1, i16 1025}
902-
// CHECK-DAG: attributes #[[$NOUNWIND_READONLY]] = { convergent mustprogress nocallback nofree nounwind willreturn memory(none) }
902+
// CHECK-SPIRV-DAG: attributes #[[$NOUNWIND_READONLY]] = { convergent mustprogress nocallback nofree nounwind willreturn memory(none) }
903+
// CHECK-AMDGCN-DAG: attributes #[[$NOUNWIND_READONLY]] = { convergent mustprogress nocallback nofree nounwind willreturn memory(none) "amdgpu-waves-per-eu"="4,10" }

llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp

Lines changed: 82 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -1111,47 +1111,25 @@ struct AAAMDWavesPerEU : public AAAMDSizeRangeAttribute {
11111111
Function *F = getAssociatedFunction();
11121112
auto &InfoCache = static_cast<AMDGPUInformationCache &>(A.getInfoCache());
11131113

1114-
auto TakeRange = [&](std::pair<unsigned, unsigned> R) {
1115-
auto [Min, Max] = R;
1116-
ConstantRange Range(APInt(32, Min), APInt(32, Max + 1));
1117-
IntegerRangeState RangeState(Range);
1118-
clampStateAndIndicateChange(this->getState(), RangeState);
1119-
indicateOptimisticFixpoint();
1120-
};
1121-
1122-
std::pair<unsigned, unsigned> MaxWavesPerEURange{
1123-
1U, InfoCache.getMaxWavesPerEU(*F)};
1124-
11251114
// If the attribute exists, we will honor it if it is not the default.
11261115
if (auto Attr = InfoCache.getWavesPerEUAttr(*F)) {
1116+
std::pair<unsigned, unsigned> MaxWavesPerEURange{
1117+
1U, InfoCache.getMaxWavesPerEU(*F)};
11271118
if (*Attr != MaxWavesPerEURange) {
1128-
TakeRange(*Attr);
1119+
auto [Min, Max] = *Attr;
1120+
ConstantRange Range(APInt(32, Min), APInt(32, Max + 1));
1121+
IntegerRangeState RangeState(Range);
1122+
this->getState() = RangeState;
1123+
indicateOptimisticFixpoint();
11291124
return;
11301125
}
11311126
}
11321127

1133-
// Unlike AAAMDFlatWorkGroupSize, it's getting trickier here. Since the
1134-
// calculation of waves per EU involves flat work group size, we can't
1135-
// simply use an assumed flat work group size as a start point, because the
1136-
// update of flat work group size is in an inverse direction of waves per
1137-
// EU. However, we can still do something if it is an entry function. Since
1138-
// an entry function is a terminal node, and flat work group size either
1139-
// from attribute or default will be used anyway, we can take that value and
1140-
// calculate the waves per EU based on it. This result can't be updated by
1141-
// no means, but that could still allow us to propagate it.
1142-
if (AMDGPU::isEntryFunctionCC(F->getCallingConv())) {
1143-
std::pair<unsigned, unsigned> FlatWorkGroupSize;
1144-
if (auto Attr = InfoCache.getFlatWorkGroupSizeAttr(*F))
1145-
FlatWorkGroupSize = *Attr;
1146-
else
1147-
FlatWorkGroupSize = InfoCache.getDefaultFlatWorkGroupSize(*F);
1148-
TakeRange(InfoCache.getEffectiveWavesPerEU(*F, MaxWavesPerEURange,
1149-
FlatWorkGroupSize));
1150-
}
1128+
if (AMDGPU::isEntryFunctionCC(F->getCallingConv()))
1129+
indicatePessimisticFixpoint();
11511130
}
11521131

11531132
ChangeStatus updateImpl(Attributor &A) override {
1154-
auto &InfoCache = static_cast<AMDGPUInformationCache &>(A.getInfoCache());
11551133
ChangeStatus Change = ChangeStatus::UNCHANGED;
11561134

11571135
auto CheckCallSite = [&](AbstractCallSite CS) {
@@ -1160,24 +1138,21 @@ struct AAAMDWavesPerEU : public AAAMDSizeRangeAttribute {
11601138
LLVM_DEBUG(dbgs() << '[' << getName() << "] Call " << Caller->getName()
11611139
<< "->" << Func->getName() << '\n');
11621140

1163-
const auto *CallerInfo = A.getAAFor<AAAMDWavesPerEU>(
1141+
const auto *CallerAA = A.getAAFor<AAAMDWavesPerEU>(
11641142
*this, IRPosition::function(*Caller), DepClassTy::REQUIRED);
1165-
const auto *AssumedGroupSize = A.getAAFor<AAAMDFlatWorkGroupSize>(
1166-
*this, IRPosition::function(*Func), DepClassTy::REQUIRED);
1167-
if (!CallerInfo || !AssumedGroupSize || !CallerInfo->isValidState() ||
1168-
!AssumedGroupSize->isValidState())
1143+
if (!CallerAA || !CallerAA->isValidState())
11691144
return false;
11701145

1171-
unsigned Min, Max;
1172-
std::tie(Min, Max) = InfoCache.getEffectiveWavesPerEU(
1173-
*Caller,
1174-
{CallerInfo->getAssumed().getLower().getZExtValue(),
1175-
CallerInfo->getAssumed().getUpper().getZExtValue() - 1},
1176-
{AssumedGroupSize->getAssumed().getLower().getZExtValue(),
1177-
AssumedGroupSize->getAssumed().getUpper().getZExtValue() - 1});
1178-
ConstantRange CallerRange(APInt(32, Min), APInt(32, Max + 1));
1179-
IntegerRangeState CallerRangeState(CallerRange);
1180-
Change |= clampStateAndIndicateChange(this->getState(), CallerRangeState);
1146+
auto Assumed = this->getAssumed();
1147+
unsigned Min = std::max(Assumed.getLower().getZExtValue(),
1148+
CallerAA->getAssumed().getLower().getZExtValue());
1149+
unsigned Max = std::max(Assumed.getUpper().getZExtValue(),
1150+
CallerAA->getAssumed().getUpper().getZExtValue());
1151+
ConstantRange Range(APInt(32, Min), APInt(32, Max));
1152+
IntegerRangeState RangeState(Range);
1153+
this->getState() = RangeState;
1154+
Change |= this->getState() == Assumed ? ChangeStatus::UNCHANGED
1155+
: ChangeStatus::CHANGED;
11811156

11821157
return true;
11831158
};
@@ -1336,6 +1311,59 @@ static void addPreloadKernArgHint(Function &F, TargetMachine &TM) {
13361311
}
13371312
}
13381313

1314+
static void checkWavesPerEU(Module &M, TargetMachine &TM) {
1315+
for (Function &F : M) {
1316+
const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F);
1317+
1318+
auto FlatWgrpSizeAttr =
1319+
AMDGPU::getIntegerPairAttribute(F, "amdgpu-flat-work-group-size");
1320+
auto WavesPerEUAttr = AMDGPU::getIntegerPairAttribute(
1321+
F, "amdgpu-waves-per-eu", /*OnlyFirstRequired=*/true);
1322+
1323+
unsigned MinWavesPerEU = ST.getMinWavesPerEU();
1324+
unsigned MaxWavesPerEU = ST.getMaxWavesPerEU();
1325+
1326+
unsigned MinFlatWgrpSize = 1U;
1327+
unsigned MaxFlatWgrpSize = 1024U;
1328+
if (FlatWgrpSizeAttr.has_value()) {
1329+
MinFlatWgrpSize = FlatWgrpSizeAttr->first;
1330+
MaxFlatWgrpSize = *(FlatWgrpSizeAttr->second);
1331+
}
1332+
1333+
// Start with the max range.
1334+
unsigned Min = MinWavesPerEU;
1335+
unsigned Max = MaxWavesPerEU;
1336+
1337+
// If the attribute exists, set them to the value from the attribute.
1338+
if (WavesPerEUAttr.has_value()) {
1339+
Min = WavesPerEUAttr->first;
1340+
if (WavesPerEUAttr->second.has_value())
1341+
Max = *(WavesPerEUAttr->second);
1342+
}
1343+
1344+
// Compute the range from flat workgroup size.
1345+
auto [MinFromFlatWgrpSize, MaxFromFlatWgrpSize] =
1346+
ST.getWavesPerEU(F, std::make_pair(MinFlatWgrpSize, MaxFlatWgrpSize));
1347+
1348+
// For the lower bound, we have to "tighten" it.
1349+
Min = std::max(Min, MinFromFlatWgrpSize);
1350+
// For the upper bound, we have to "extend" it.
1351+
Max = std::max(Max, MaxFromFlatWgrpSize);
1352+
1353+
// Clamp the range to the max range.
1354+
Min = std::max(Min, MinWavesPerEU);
1355+
Max = std::min(Max, MaxWavesPerEU);
1356+
1357+
// Update the attribute if it is not the max.
1358+
if (Min != MinWavesPerEU || Max != MaxWavesPerEU) {
1359+
SmallString<10> Buffer;
1360+
raw_svector_ostream OS(Buffer);
1361+
OS << Min << ',' << Max;
1362+
F.addFnAttr("amdgpu-waves-per-eu", OS.str());
1363+
}
1364+
}
1365+
}
1366+
13391367
static bool runImpl(Module &M, AnalysisGetter &AG, TargetMachine &TM,
13401368
AMDGPUAttributorOptions Options,
13411369
ThinOrFullLTOPhase LTOPhase) {
@@ -1425,8 +1453,14 @@ static bool runImpl(Module &M, AnalysisGetter &AG, TargetMachine &TM,
14251453
}
14261454
}
14271455

1428-
ChangeStatus Change = A.run();
1429-
return Change == ChangeStatus::CHANGED;
1456+
bool Changed = A.run() == ChangeStatus::CHANGED;
1457+
1458+
if (Changed && (LTOPhase == ThinOrFullLTOPhase::None ||
1459+
LTOPhase == ThinOrFullLTOPhase::FullLTOPostLink ||
1460+
LTOPhase == ThinOrFullLTOPhase::ThinLTOPostLink))
1461+
checkWavesPerEU(M, TM);
1462+
1463+
return Changed;
14301464
}
14311465

14321466
class AMDGPUAttributorLegacy : public ModulePass {

llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -4,17 +4,17 @@
44

55
declare void @llvm.memcpy.p1.p4.i32(ptr addrspace(1) nocapture, ptr addrspace(4) nocapture, i32, i1) #0
66

7-
@lds.i32 = unnamed_addr addrspace(3) global i32 poison, align 4
8-
@lds.arr = unnamed_addr addrspace(3) global [256 x i32] poison, align 4
7+
@lds.i32 = unnamed_addr addrspace(3) global i32 undef, align 4
8+
@lds.arr = unnamed_addr addrspace(3) global [256 x i32] undef, align 4
99

10-
@global.i32 = unnamed_addr addrspace(1) global i32 poison, align 4
11-
@global.arr = unnamed_addr addrspace(1) global [256 x i32] poison, align 4
10+
@global.i32 = unnamed_addr addrspace(1) global i32 undef, align 4
11+
@global.arr = unnamed_addr addrspace(1) global [256 x i32] undef, align 4
1212

1313
;.
14-
; HSA: @lds.i32 = unnamed_addr addrspace(3) global i32 poison, align 4
15-
; HSA: @lds.arr = unnamed_addr addrspace(3) global [256 x i32] poison, align 4
16-
; HSA: @global.i32 = unnamed_addr addrspace(1) global i32 poison, align 4
17-
; HSA: @global.arr = unnamed_addr addrspace(1) global [256 x i32] poison, align 4
14+
; HSA: @lds.i32 = unnamed_addr addrspace(3) global i32 undef, align 4
15+
; HSA: @lds.arr = unnamed_addr addrspace(3) global [256 x i32] undef, align 4
16+
; HSA: @global.i32 = unnamed_addr addrspace(1) global i32 undef, align 4
17+
; HSA: @global.arr = unnamed_addr addrspace(1) global [256 x i32] undef, align 4
1818
;.
1919
define amdgpu_kernel void @store_cast_0_flat_to_group_addrspacecast() #1 {
2020
; HSA-LABEL: define {{[^@]+}}@store_cast_0_flat_to_group_addrspacecast
@@ -232,9 +232,9 @@ attributes #1 = { nounwind }
232232
; AKF_HSA: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
233233
; AKF_HSA: attributes #[[ATTR1]] = { nounwind }
234234
;.
235-
; ATTRIBUTOR_HSA: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
236-
; ATTRIBUTOR_HSA: attributes #[[ATTR1]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
237-
; ATTRIBUTOR_HSA: attributes #[[ATTR2]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
235+
; ATTRIBUTOR_HSA: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) "amdgpu-waves-per-eu"="4,10" }
236+
; ATTRIBUTOR_HSA: attributes #[[ATTR1]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
237+
; ATTRIBUTOR_HSA: attributes #[[ATTR2]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
238238
;.
239239
; AKF_HSA: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 500}
240240
;.

llvm/test/CodeGen/AMDGPU/amdgpu-attributor-no-agpr.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -252,13 +252,13 @@ define amdgpu_kernel void @indirect_calls_none_agpr(i1 %cond) {
252252
}
253253

254254

255-
attributes #0 = { "amdgpu-agpr-alloc"="0" }
255+
attributes #0 = { "amdgpu-no-agpr" }
256256
;.
257-
; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx90a" "uniform-work-group-size"="false" }
258-
; CHECK: attributes #[[ATTR1]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx90a" "uniform-work-group-size"="false" }
259-
; CHECK: attributes #[[ATTR2]] = { "target-cpu"="gfx90a" "uniform-work-group-size"="false" }
260-
; CHECK: attributes #[[ATTR3:[0-9]+]] = { convergent nocallback nofree nosync nounwind willreturn memory(none) "target-cpu"="gfx90a" }
261-
; CHECK: attributes #[[ATTR4:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) "target-cpu"="gfx90a" }
262-
; CHECK: attributes #[[ATTR5:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) "target-cpu"="gfx90a" }
263-
; CHECK: attributes #[[ATTR6]] = { "amdgpu-agpr-alloc"="0" }
257+
; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,8" "target-cpu"="gfx90a" "uniform-work-group-size"="false" }
258+
; CHECK: attributes #[[ATTR1]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,8" "target-cpu"="gfx90a" "uniform-work-group-size"="false" }
259+
; CHECK: attributes #[[ATTR2]] = { "amdgpu-waves-per-eu"="4,8" "target-cpu"="gfx90a" "uniform-work-group-size"="false" }
260+
; CHECK: attributes #[[ATTR3:[0-9]+]] = { convergent nocallback nofree nosync nounwind willreturn memory(none) "amdgpu-waves-per-eu"="4,8" "target-cpu"="gfx90a" }
261+
; CHECK: attributes #[[ATTR4:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) "amdgpu-waves-per-eu"="4,8" "target-cpu"="gfx90a" }
262+
; CHECK: attributes #[[ATTR5:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) "amdgpu-waves-per-eu"="4,8" "target-cpu"="gfx90a" }
263+
; CHECK: attributes #[[ATTR6]] = { "amdgpu-no-agpr" }
264264
;.

llvm/test/CodeGen/AMDGPU/annotate-existing-abi-attributes.ll

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -117,14 +117,14 @@ define void @call_no_dispatch_id() {
117117
ret void
118118
}
119119
;.
120-
; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-workitem-id-x" "uniform-work-group-size"="false" }
121-
; CHECK: attributes #[[ATTR1]] = { "amdgpu-no-workitem-id-y" "uniform-work-group-size"="false" }
122-
; CHECK: attributes #[[ATTR2]] = { "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
123-
; CHECK: attributes #[[ATTR3]] = { "amdgpu-no-workgroup-id-x" "uniform-work-group-size"="false" }
124-
; CHECK: attributes #[[ATTR4]] = { "amdgpu-no-workgroup-id-y" "uniform-work-group-size"="false" }
125-
; CHECK: attributes #[[ATTR5]] = { "amdgpu-no-workgroup-id-z" "uniform-work-group-size"="false" }
126-
; CHECK: attributes #[[ATTR6]] = { "amdgpu-no-dispatch-ptr" "uniform-work-group-size"="false" }
127-
; CHECK: attributes #[[ATTR7]] = { "amdgpu-no-queue-ptr" "uniform-work-group-size"="false" }
128-
; CHECK: attributes #[[ATTR8]] = { "amdgpu-no-implicitarg-ptr" "uniform-work-group-size"="false" }
129-
; CHECK: attributes #[[ATTR9]] = { "amdgpu-no-dispatch-id" "uniform-work-group-size"="false" }
120+
; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-workitem-id-x" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
121+
; CHECK: attributes #[[ATTR1]] = { "amdgpu-no-workitem-id-y" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
122+
; CHECK: attributes #[[ATTR2]] = { "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
123+
; CHECK: attributes #[[ATTR3]] = { "amdgpu-no-workgroup-id-x" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
124+
; CHECK: attributes #[[ATTR4]] = { "amdgpu-no-workgroup-id-y" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
125+
; CHECK: attributes #[[ATTR5]] = { "amdgpu-no-workgroup-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
126+
; CHECK: attributes #[[ATTR6]] = { "amdgpu-no-dispatch-ptr" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
127+
; CHECK: attributes #[[ATTR7]] = { "amdgpu-no-queue-ptr" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
128+
; CHECK: attributes #[[ATTR8]] = { "amdgpu-no-implicitarg-ptr" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
129+
; CHECK: attributes #[[ATTR9]] = { "amdgpu-no-dispatch-id" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
130130
;.

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