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JonPsson1JonPsson1
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Try in common code.
In SystemZ only. Try removeing callseq instructions. was 741b28ae
1 parent 4ea5c60 commit 71ee77a

12 files changed

+45
-31
lines changed

‎llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8096,6 +8096,24 @@ static void createPHIsForSelects(SmallVector<MachineInstr*, 8> &Selects,
80968096
MF->getProperties().reset(MachineFunctionProperties::Property::NoPHIs);
80978097
}
80988098

8099+
MachineBasicBlock *
8100+
SystemZTargetLowering::emitAdjCallStack(MachineInstr &MI,
8101+
MachineBasicBlock *BB) const {
8102+
// Do the work of MachineFrameInfo::computeMaxCallFrameSize() early and
8103+
// remove these nodes. Given that these nodes start out as a glued sequence
8104+
// it seems best to remove them here after instruction selection and
8105+
// scheduling. NB: MIR testing does not work (yet) for call frames with
8106+
// this.
8107+
MachineFrameInfo &MFI = BB->getParent()->getFrameInfo();
8108+
uint32_t NumBytes = MI.getOperand(0).getImm();
8109+
if (NumBytes > MFI.getMaxCallFrameSize())
8110+
MFI.setMaxCallFrameSize(NumBytes);
8111+
MFI.setAdjustsStack(true);
8112+
8113+
MI.eraseFromParent();
8114+
return BB;
8115+
}
8116+
80998117
// Implement EmitInstrWithCustomInserter for pseudo Select* instruction MI.
81008118
MachineBasicBlock *
81018119
SystemZTargetLowering::emitSelect(MachineInstr &MI,
@@ -9299,6 +9317,10 @@ getBackchainAddress(SDValue SP, SelectionDAG &DAG) const {
92999317
MachineBasicBlock *SystemZTargetLowering::EmitInstrWithCustomInserter(
93009318
MachineInstr &MI, MachineBasicBlock *MBB) const {
93019319
switch (MI.getOpcode()) {
9320+
case SystemZ::ADJCALLSTACKDOWN:
9321+
case SystemZ::ADJCALLSTACKUP:
9322+
return emitAdjCallStack(MI, MBB);
9323+
93029324
case SystemZ::Select32:
93039325
case SystemZ::Select64:
93049326
case SystemZ::Select128:

‎llvm/lib/Target/SystemZ/SystemZISelLowering.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -755,6 +755,8 @@ class SystemZTargetLowering : public TargetLowering {
755755
MachineBasicBlock *Target) const;
756756

757757
// Implement EmitInstrWithCustomInserter for individual operation types.
758+
MachineBasicBlock *emitAdjCallStack(MachineInstr &MI,
759+
MachineBasicBlock *BB) const;
758760
MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB) const;
759761
MachineBasicBlock *emitCondStore(MachineInstr &MI, MachineBasicBlock *BB,
760762
unsigned StoreOpcode, unsigned STOCOpcode,

‎llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ static uint64_t allOnes(unsigned int Count) {
5959
void SystemZInstrInfo::anchor() {}
6060

6161
SystemZInstrInfo::SystemZInstrInfo(SystemZSubtarget &sti)
62-
: SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
62+
: SystemZGenInstrInfo(-1, -1),
6363
RI(sti.getSpecialRegisters()->getReturnFunctionAddressRegister()),
6464
STI(sti) {}
6565

‎llvm/lib/Target/SystemZ/SystemZInstrInfo.td

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -13,9 +13,10 @@ def IsTargetELF : Predicate<"Subtarget->isTargetELF()">;
1313
// Stack allocation
1414
//===----------------------------------------------------------------------===//
1515

16-
// The callseq_start node requires the hasSideEffects flag, even though these
17-
// instructions are noops on SystemZ.
18-
let hasNoSchedulingInfo = 1, hasSideEffects = 1 in {
16+
// These pseudos are removed after instruction selection while updating the
17+
// values of MaxcallFrameSize and AdjustsStack which are needed during frame
18+
// lowering. The callseq_start node requires the hasSideEffects flag.
19+
let usesCustomInserter = 1, hasNoSchedulingInfo = 1, hasSideEffects = 1 in {
1920
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
2021
[(callseq_start timm:$amt1, timm:$amt2)]>;
2122
def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),

‎llvm/test/CodeGen/SystemZ/call-zos-vararg.ll

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -88,13 +88,16 @@ entry:
8888
ret i64 %retval
8989
}
9090

91+
; TODO: Unfortunately the lgdr is scheduled below the COPY from $r1d, causing
92+
; an overlap and thus an extra copy.
9193
; CHECK-LABEL: call_vararg_both0:
9294
; CHECK: stmg 6, 7, 1872(4)
9395
; CHECK-NEXT: aghi 4, -192
9496
; CHECK-NEXT: lg 6, 40(5)
9597
; CHECK-NEXT: lg 5, 32(5)
98+
; CHECK-NEXT: lgdr 0, 0
9699
; CHECK-NEXT: lgr 2, 1
97-
; CHECK-NEXT: lgdr 1, 0
100+
; CHECK-NEXT: lgr 1, 0
98101
; CHECK-NEXT: basr 7, 6
99102
; CHECK-NEXT: bcr 0, 0
100103
; CHECK-NEXT: lg 7, 2072(4)

‎llvm/test/CodeGen/SystemZ/cond-move-04.mir

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -64,12 +64,10 @@ body: |
6464
CHIMux %3, 0, implicit-def $cc
6565
%0 = LOCRMux undef %0, %5, 14, 6, implicit $cc
6666
%0 = LOCRMux %0, %2, 14, 6, implicit killed $cc
67-
ADJCALLSTACKDOWN 0, 0
6867
%7 = LGFR %0
6968
$r3d = LGHI 0
7069
$r4d = COPY %7
7170
CallBRASL @foo, undef $r2d, killed $r3d, killed $r4d, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc, implicit-def dead $r2d
72-
ADJCALLSTACKUP 0, 0
7371
J %bb.1
7472
7573
...

‎llvm/test/CodeGen/SystemZ/cond-move-08.mir

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -154,9 +154,7 @@ body: |
154154
J %bb.4
155155
156156
bb.4.bb33:
157-
ADJCALLSTACKDOWN 0, 0
158157
CallBRASL @fun, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc
159-
ADJCALLSTACKUP 0, 0
160158
STRL %4, @globvar :: (store (s32) into @globvar)
161159
CLFIMux undef %23:grx32bit, 1, implicit-def $cc
162160
%25:grx32bit = LHIMux 0

‎llvm/test/CodeGen/SystemZ/cond-move-regalloc-hints-02.mir

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -44,11 +44,9 @@ body: |
4444
%11:gr32bit = SELRMux %8, %9:grx32bit, 14, 6, implicit killed $cc
4545
CHIMux %6, 2, implicit-def $cc
4646
%0:gr32bit = SELRMux %11, %5, 14, 8, implicit killed $cc
47-
ADJCALLSTACKDOWN 0, 0
4847
%10:gr64bit = LGFR %0
4948
$r2d = COPY %10
5049
CallBRASL @foo, killed $r2d, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc, implicit $fpc
51-
ADJCALLSTACKUP 0, 0
5250
J %bb.1
5351
5452
...

‎llvm/test/CodeGen/SystemZ/cond-move-regalloc-hints.mir

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -199,18 +199,12 @@ body: |
199199
200200
%32:gr64bit = COPY $r3d
201201
%0:gr64bit = COPY $r2d
202-
ADJCALLSTACKDOWN 0, 0
203202
CallBRASL @sre_malloc, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc, implicit-def $r2d
204203
%1:addr64bit = COPY $r2d
205-
ADJCALLSTACKUP 0, 0
206-
ADJCALLSTACKDOWN 0, 0
207204
CallBRASL @sre_malloc, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc, implicit-def $r2d
208205
%2:addr64bit = COPY $r2d
209-
ADJCALLSTACKUP 0, 0
210206
%3:gr32bit = AHIMuxK %0.subreg_l32, -1, implicit-def dead $cc
211-
ADJCALLSTACKDOWN 0, 0
212207
CallBRASL @malloc, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc
213-
ADJCALLSTACKUP 0, 0
214208
%55:gr32bit = AHIMuxK %0.subreg_l32, 3, implicit-def dead $cc
215209
%56:addr64bit = LGHI 0
216210
%57:gr64bit = COPY %0

‎llvm/test/CodeGen/SystemZ/frame-28.mir

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -177,9 +177,7 @@ body: |
177177
VST64 renamable $f16d, %stack.0, 0, $noreg
178178
VST64 renamable $f16d, %stack.0, 0, $noreg
179179
VST64 renamable $f16d, %stack.1, 0, $noreg
180-
ADJCALLSTACKDOWN 0, 0
181180
CallBRASL @foo, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc, implicit $fpc, implicit-def $r2l
182-
ADJCALLSTACKUP 0, 0
183181
$f17d = IMPLICIT_DEF
184182
VST64 renamable $f17d, %stack.1, 0, $noreg
185183
Return

‎llvm/test/CodeGen/SystemZ/swifterror.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -30,8 +30,8 @@ entry:
3030
define float @caller(ptr %error_ref) {
3131
; CHECK-LABEL: caller:
3232
; Make a copy of error_ref because r2 is getting clobbered
33-
; CHECK: lgr %r[[REG1:[0-9]+]], %r2
34-
; CHECK: lghi %r9, 0
33+
; CHECK-DAG: lgr %r[[REG1:[0-9]+]], %r2
34+
; CHECK-DAG: lghi %r9, 0
3535
; CHECK: brasl %r14, foo
3636
; CHECK: %r2, %r9
3737
; CHECK: jlh
@@ -197,7 +197,7 @@ define void @foo_sret(ptr sret(%struct.S) %agg.result, i32 %val1, ptr swifterror
197197
; CHECK-LABEL: foo_sret:
198198
; CHECK-DAG: lgr %r[[REG1:[0-9]+]], %r2
199199
; CHECK-DAG: lr %r[[REG2:[0-9]+]], %r3
200-
; CHECK: lghi %r2, 16
200+
; CHECK-DAG: lghi %r2, 16
201201
; CHECK: brasl %r14, malloc
202202
; CHECK: mvi 8(%r2), 1
203203
; CHECK: st %r[[REG2]], 4(%r[[REG1]])
@@ -280,7 +280,7 @@ define float @caller_with_multiple_swifterror_values(ptr %error_ref, ptr %error_
280280
; CHECK-DAG: lgr %r[[REG1:[0-9]+]], %r2
281281
; CHECK-DAG: lgr %r[[REG2:[0-9]+]], %r3
282282
; The first swifterror value:
283-
; CHECK: lghi %r9, 0
283+
; CHECK-DAG: lghi %r9, 0
284284
; CHECK: brasl %r14, foo
285285
; CHECK: ltgr %r2, %r9
286286
; CHECK: jlh

‎llvm/test/CodeGen/SystemZ/vector-constrained-fp-intrinsics.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1649,8 +1649,8 @@ define <2 x double> @constrained_vector_powi_v2f64() #0 {
16491649
; S390X-NEXT: brasl %r14, __powidf2@PLT
16501650
; S390X-NEXT: larl %r1, .LCPI36_1
16511651
; S390X-NEXT: ld %f1, 0(%r1)
1652-
; S390X-NEXT: ldr %f8, %f0
16531652
; S390X-NEXT: lghi %r2, 3
1653+
; S390X-NEXT: ldr %f8, %f0
16541654
; S390X-NEXT: ldr %f0, %f1
16551655
; S390X-NEXT: brasl %r14, __powidf2@PLT
16561656
; S390X-NEXT: ldr %f2, %f8
@@ -1707,14 +1707,14 @@ define <3 x float> @constrained_vector_powi_v3f32() #0 {
17071707
; S390X-NEXT: brasl %r14, __powisf2@PLT
17081708
; S390X-NEXT: larl %r1, .LCPI37_1
17091709
; S390X-NEXT: le %f1, 0(%r1)
1710-
; S390X-NEXT: ler %f8, %f0
17111710
; S390X-NEXT: lghi %r2, 3
1711+
; S390X-NEXT: ler %f8, %f0
17121712
; S390X-NEXT: ler %f0, %f1
17131713
; S390X-NEXT: brasl %r14, __powisf2@PLT
17141714
; S390X-NEXT: larl %r1, .LCPI37_2
17151715
; S390X-NEXT: le %f1, 0(%r1)
1716-
; S390X-NEXT: ler %f9, %f0
17171716
; S390X-NEXT: lghi %r2, 3
1717+
; S390X-NEXT: ler %f9, %f0
17181718
; S390X-NEXT: ler %f0, %f1
17191719
; S390X-NEXT: brasl %r14, __powisf2@PLT
17201720
; S390X-NEXT: ler %f2, %f9
@@ -1784,14 +1784,14 @@ define void @constrained_vector_powi_v3f64(ptr %a) #0 {
17841784
; S390X-NEXT: brasl %r14, __powidf2@PLT
17851785
; S390X-NEXT: larl %r1, .LCPI38_1
17861786
; S390X-NEXT: ld %f1, 0(%r1)
1787-
; S390X-NEXT: ldr %f8, %f0
17881787
; S390X-NEXT: lghi %r2, 3
1788+
; S390X-NEXT: ldr %f8, %f0
17891789
; S390X-NEXT: ldr %f0, %f1
17901790
; S390X-NEXT: brasl %r14, __powidf2@PLT
17911791
; S390X-NEXT: larl %r1, .LCPI38_2
17921792
; S390X-NEXT: ld %f1, 0(%r1)
1793-
; S390X-NEXT: ldr %f9, %f0
17941793
; S390X-NEXT: lghi %r2, 3
1794+
; S390X-NEXT: ldr %f9, %f0
17951795
; S390X-NEXT: ldr %f0, %f1
17961796
; S390X-NEXT: brasl %r14, __powidf2@PLT
17971797
; S390X-NEXT: std %f0, 16(%r13)
@@ -1865,20 +1865,20 @@ define <4 x double> @constrained_vector_powi_v4f64() #0 {
18651865
; S390X-NEXT: brasl %r14, __powidf2@PLT
18661866
; S390X-NEXT: larl %r1, .LCPI39_1
18671867
; S390X-NEXT: ld %f1, 0(%r1)
1868-
; S390X-NEXT: ldr %f8, %f0
18691868
; S390X-NEXT: lghi %r2, 3
1869+
; S390X-NEXT: ldr %f8, %f0
18701870
; S390X-NEXT: ldr %f0, %f1
18711871
; S390X-NEXT: brasl %r14, __powidf2@PLT
18721872
; S390X-NEXT: larl %r1, .LCPI39_2
18731873
; S390X-NEXT: ld %f1, 0(%r1)
1874-
; S390X-NEXT: ldr %f9, %f0
18751874
; S390X-NEXT: lghi %r2, 3
1875+
; S390X-NEXT: ldr %f9, %f0
18761876
; S390X-NEXT: ldr %f0, %f1
18771877
; S390X-NEXT: brasl %r14, __powidf2@PLT
18781878
; S390X-NEXT: larl %r1, .LCPI39_3
18791879
; S390X-NEXT: ld %f1, 0(%r1)
1880-
; S390X-NEXT: ldr %f10, %f0
18811880
; S390X-NEXT: lghi %r2, 3
1881+
; S390X-NEXT: ldr %f10, %f0
18821882
; S390X-NEXT: ldr %f0, %f1
18831883
; S390X-NEXT: brasl %r14, __powidf2@PLT
18841884
; S390X-NEXT: ldr %f2, %f10

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