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[RISCV] Add Smaia and Ssaia extensions support
This patch implements 1.0-RC3: https://github.com/riscv/riscv-aia/releases/download/1.0-RC3/riscv-interrupts-1.0-RC3.pdf Differential Revision: https://reviews.llvm.org/D148066
1 parent 4e4db6f commit 74c1fa6

15 files changed

+601
-12
lines changed

‎clang/test/Preprocessor/riscv-target-features.c

+18
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,8 @@
6363
// CHECK-NOT: __riscv_zvksh {{.*$}}
6464
// CHECK-NOT: __riscv_zvkt {{.*$}}
6565
// CHECK-NOT: __riscv_zicond {{.*$}}
66+
// CHECK-NOT: __riscv_smaia {{.*$}}
67+
// CHECK-NOT: __riscv_ssaia {{.*$}}
6668

6769
// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
6870
// RUN: -o - | FileCheck %s
@@ -640,3 +642,19 @@
640642
// RUN: -march=rv64i_zicond1p0 -x c -E -dM %s \
641643
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICOND-EXT %s
642644
// CHECK-ZICOND-EXT: __riscv_zicond 1000000{{$}}
645+
646+
// RUN: %clang -target riscv32 -menable-experimental-extensions \
647+
// RUN: -march=rv32ismaia1p0 -x c -E -dM %s \
648+
// RUN: -o - | FileCheck --check-prefix=CHECK-SMAIA-EXT %s
649+
// RUN: %clang -target riscv64 -menable-experimental-extensions \
650+
// RUN: -march=rv64ismaia1p0 -x c -E -dM %s \
651+
// RUN: -o - | FileCheck --check-prefix=CHECK-SMAIA-EXT %s
652+
// CHECK-SMAIA-EXT: __riscv_smaia 1000000{{$}}
653+
654+
// RUN: %clang -target riscv32 -menable-experimental-extensions \
655+
// RUN: -march=rv32issaia1p0 -x c -E -dM %s \
656+
// RUN: -o - | FileCheck --check-prefix=CHECK-SSAIA-EXT %s
657+
// RUN: %clang -target riscv64 -menable-experimental-extensions \
658+
// RUN: -march=rv64issaia1p0 -x c -E -dM %s \
659+
// RUN: -o - | FileCheck --check-prefix=CHECK-SSAIA-EXT %s
660+
// CHECK-SSAIA-EXT: __riscv_ssaia 1000000{{$}}

‎llvm/docs/RISCVUsage.rst

+6
Original file line numberDiff line numberDiff line change
@@ -177,6 +177,12 @@ LLVM supports (to various degrees) a number of experimental extensions. All exp
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178178
The primary goal of experimental support is to assist in the process of ratification by providing an existence proof of an implementation, and simplifying efforts to validate the value of a proposed extension against large code bases. Experimental extensions are expected to either transition to ratified status, or be eventually removed. The decision on whether to accept an experimental extension is currently done on an entirely case by case basis; if you want to propose one, attending the bi-weekly RISC-V sync-up call is strongly advised.
179179

180+
``experimental-smaia``
181+
LLVM implements the `Ratification candidate 3 <https://github.com/riscv/riscv-aia/releases/tag/1.0-RC3>`_.
182+
183+
``experimental-ssaia``
184+
LLVM implements the `Ratification candidate 3 <https://github.com/riscv/riscv-aia/releases/tag/1.0-RC3>`_.
185+
180186
``experimental-zca``
181187
LLVM implements the `1.0.1 draft specification <https://github.com/riscv/riscv-code-size-reduction/releases/tag/v1.0.1>`__.
182188

‎llvm/lib/Support/RISCVISAInfo.cpp

+3
Original file line numberDiff line numberDiff line change
@@ -135,6 +135,9 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
135135
};
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137137
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
138+
{"smaia", RISCVExtensionVersion{1, 0}},
139+
{"ssaia", RISCVExtensionVersion{1, 0}},
140+
138141
{"zihintntl", RISCVExtensionVersion{0, 2}},
139142

140143
{"zca", RISCVExtensionVersion{1, 0}},

‎llvm/lib/Target/RISCV/RISCVFeatures.td

+13
Original file line numberDiff line numberDiff line change
@@ -576,6 +576,19 @@ def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
576576
AssemblerPredicate<(all_of FeatureStdExtZicond),
577577
"'Zicond' (Integer Conditional Operations)">;
578578

579+
def FeatureStdExtSmaia
580+
: SubtargetFeature<"experimental-smaia", "HasStdExtSmaia", "true",
581+
"'Smaia' (Smaia encompasses all added CSRs and all "
582+
"modifications to interrupt response behavior that the "
583+
"AIA specifies for a hart, over all privilege levels.)",
584+
[]>;
585+
586+
def FeatureStdExtSsaia
587+
: SubtargetFeature<"experimental-ssaia", "HasStdExtSsaia", "true",
588+
"'Ssaia' (Ssaia is essentially the same as Smaia except "
589+
"excluding the machine-level CSRs and behavior not "
590+
"directly visible to supervisor level.)", []>;
591+
579592
//===----------------------------------------------------------------------===//
580593
// Vendor extensions
581594
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVSystemOperands.td

+48
Original file line numberDiff line numberDiff line change
@@ -359,3 +359,51 @@ foreach i = 0...3 in {
359359
//===-----------------------------------------------
360360

361361
def SEED : SysReg<"seed", 0x015>;
362+
363+
//===-----------------------------------------------
364+
// Advanced Interrupt Architecture
365+
//===-----------------------------------------------
366+
367+
// Machine-level CSRs
368+
def : SysReg<"miselect", 0x350>;
369+
def : SysReg<"mireg", 0x351>;
370+
def : SysReg<"mtopei", 0x35C>;
371+
def : SysReg<"mtopi", 0xFB0>;
372+
def : SysReg<"mvien", 0x308>;
373+
def : SysReg<"mvip", 0x309>;
374+
let isRV32Only = 1 in {
375+
def : SysReg<"midelegh", 0x313>;
376+
def : SysReg<"mieh", 0x314>;
377+
def : SysReg<"mvienh", 0x318>;
378+
def : SysReg<"mviph", 0x319>;
379+
def : SysReg<"miph", 0x354>;
380+
} // isRV32Only
381+
382+
// Supervisor-level CSRs
383+
def : SysReg<"siselect", 0x150>;
384+
def : SysReg<"sireg", 0x151>;
385+
def : SysReg<"stopei", 0x15C>;
386+
def : SysReg<"stopi", 0xDB0>;
387+
let isRV32Only = 1 in {
388+
def : SysReg<"sieh", 0x114>;
389+
def : SysReg<"siph", 0x154>;
390+
} // isRV32Only
391+
392+
// Hypervisor and VS CSRs
393+
def : SysReg<"hvien", 0x608>;
394+
def : SysReg<"hvictl", 0x609>;
395+
def : SysReg<"hviprio1", 0x646>;
396+
def : SysReg<"hviprio2", 0x647>;
397+
def : SysReg<"vsiselect", 0x250>;
398+
def : SysReg<"vsireg", 0x251>;
399+
def : SysReg<"vstopei", 0x25C>;
400+
def : SysReg<"vstopi", 0xEB0>;
401+
let isRV32Only = 1 in {
402+
def : SysReg<"hidelegh", 0x613>;
403+
def : SysReg<"hvienh", 0x618>;
404+
def : SysReg<"hviph", 0x655>;
405+
def : SysReg<"hviprio1h", 0x656>;
406+
def : SysReg<"hviprio2h", 0x657>;
407+
def : SysReg<"vsieh", 0x214>;
408+
def : SysReg<"vsiph", 0x254>;
409+
} // isRV32Only

‎llvm/test/CodeGen/RISCV/attributes.ll

+8
Original file line numberDiff line numberDiff line change
@@ -71,6 +71,8 @@
7171
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s
7272
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkt %s -o - | FileCheck --check-prefix=RV32ZVKT %s
7373
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s
74+
; RUN: llc -mtriple=riscv32 -mattr=+experimental-smaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SMAIA %s
75+
; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SSAIA %s
7476

7577
; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
7678
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
@@ -149,6 +151,8 @@
149151
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s
150152
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkt %s -o - | FileCheck --check-prefix=RV64ZVKT %s
151153
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s
154+
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SMAIA %s
155+
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SSAIA %s
152156

153157
; CHECK: .attribute 4, 16
154158

@@ -222,6 +226,8 @@
222226
; RV32ZVKSH: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh0p5_zvl32b1p0"
223227
; RV32ZVKT: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkt0p5_zvl32b1p0"
224228
; RV32ZICOND: .attribute 5, "rv32i2p1_zicond1p0"
229+
; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0"
230+
; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
225231

226232
; RV64M: .attribute 5, "rv64i2p1_m2p0"
227233
; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"
@@ -299,6 +305,8 @@
299305
; RV64ZVKSH: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksh0p5_zvl32b1p0"
300306
; RV64ZVKT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkt0p5_zvl32b1p0"
301307
; RV64ZICOND: .attribute 5, "rv64i2p1_zicond1p0"
308+
; RV64SMAIA: .attribute 5, "rv64i2p1_smaia1p0"
309+
; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
302310

303311
define i32 @addi(i32 %a) {
304312
%1 = add i32 %a, 1

‎llvm/test/MC/RISCV/attribute-arch.s

+6
Original file line numberDiff line numberDiff line change
@@ -251,3 +251,9 @@
251251

252252
.attribute arch, "rv32izicond1p0"
253253
# CHECK: attribute 5, "rv32i2p1_zicond1p0"
254+
255+
.attribute arch, "rv32i_smaia1p0"
256+
# CHECK: attribute 5, "rv32i2p1_smaia1p0"
257+
258+
.attribute arch, "rv32i_ssaia1p0"
259+
# CHECK: attribute 5, "rv32i2p1_ssaia1p0"

‎llvm/test/MC/RISCV/hypervisor-csr-names.s

+116
Original file line numberDiff line numberDiff line change
@@ -447,3 +447,119 @@ csrrs t2, 0x60E, zero
447447
csrrs t1, hstateen3, zero
448448
# uimm12
449449
csrrs t2, 0x60F, zero
450+
451+
#########################################
452+
# Advanced Interrupt Architecture (Smaia and Ssaia)
453+
#########################################
454+
455+
# hvien
456+
# name
457+
# CHECK-INST: csrrs t1, hvien, zero
458+
# CHECK-ENC: encoding: [0x73,0x23,0x80,0x60]
459+
# CHECK-INST-ALIAS: csrr t1, hvien
460+
# uimm12
461+
# CHECK-INST: csrrs t2, hvien, zero
462+
# CHECK-ENC: encoding: [0xf3,0x23,0x80,0x60]
463+
# CHECK-INST-ALIAS: csrr t2, hvien
464+
# name
465+
csrrs t1, hvien, zero
466+
# uimm12
467+
csrrs t2, 0x608, zero
468+
469+
# hvictl
470+
# name
471+
# CHECK-INST: csrrs t1, hvictl, zero
472+
# CHECK-ENC: encoding: [0x73,0x23,0x90,0x60]
473+
# CHECK-INST-ALIAS: csrr t1, hvictl
474+
# uimm12
475+
# CHECK-INST: csrrs t2, hvictl, zero
476+
# CHECK-ENC: encoding: [0xf3,0x23,0x90,0x60]
477+
# CHECK-INST-ALIAS: csrr t2, hvictl
478+
# name
479+
csrrs t1, hvictl, zero
480+
# uimm12
481+
csrrs t2, 0x609, zero
482+
483+
# hviprio1
484+
# name
485+
# CHECK-INST: csrrs t1, hviprio1, zero
486+
# CHECK-ENC: encoding: [0x73,0x23,0x60,0x64]
487+
# CHECK-INST-ALIAS: csrr t1, hviprio1
488+
# uimm12
489+
# CHECK-INST: csrrs t2, hviprio1, zero
490+
# CHECK-ENC: encoding: [0xf3,0x23,0x60,0x64]
491+
# CHECK-INST-ALIAS: csrr t2, hviprio1
492+
# name
493+
csrrs t1, hviprio1, zero
494+
# uimm12
495+
csrrs t2, 0x646, zero
496+
497+
# hviprio2
498+
# name
499+
# CHECK-INST: csrrs t1, hviprio2, zero
500+
# CHECK-ENC: encoding: [0x73,0x23,0x70,0x64]
501+
# CHECK-INST-ALIAS: csrr t1, hviprio2
502+
# uimm12
503+
# CHECK-INST: csrrs t2, hviprio2, zero
504+
# CHECK-ENC: encoding: [0xf3,0x23,0x70,0x64]
505+
# CHECK-INST-ALIAS: csrr t2, hviprio2
506+
# name
507+
csrrs t1, hviprio2, zero
508+
# uimm12
509+
csrrs t2, 0x647, zero
510+
511+
# vsiselect
512+
# name
513+
# CHECK-INST: csrrs t1, vsiselect, zero
514+
# CHECK-ENC: encoding: [0x73,0x23,0x00,0x25]
515+
# CHECK-INST-ALIAS: csrr t1, vsiselect
516+
# uimm12
517+
# CHECK-INST: csrrs t2, vsiselect, zero
518+
# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x25]
519+
# CHECK-INST-ALIAS: csrr t2, vsiselect
520+
# name
521+
csrrs t1, vsiselect, zero
522+
# uimm12
523+
csrrs t2, 0x250, zero
524+
525+
# vsireg
526+
# name
527+
# CHECK-INST: csrrs t1, vsireg, zero
528+
# CHECK-ENC: encoding: [0x73,0x23,0x10,0x25]
529+
# CHECK-INST-ALIAS: csrr t1, vsireg
530+
# uimm12
531+
# CHECK-INST: csrrs t2, vsireg, zero
532+
# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x25]
533+
# CHECK-INST-ALIAS: csrr t2, vsireg
534+
# name
535+
csrrs t1, vsireg, zero
536+
# uimm12
537+
csrrs t2, 0x251, zero
538+
539+
# vstopei
540+
# name
541+
# CHECK-INST: csrrs t1, vstopei, zero
542+
# CHECK-ENC: encoding: [0x73,0x23,0xc0,0x25]
543+
# CHECK-INST-ALIAS: csrr t1, vstopei
544+
# uimm12
545+
# CHECK-INST: csrrs t2, vstopei, zero
546+
# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x25]
547+
# CHECK-INST-ALIAS: csrr t2, vstopei
548+
# name
549+
csrrs t1, vstopei, zero
550+
# uimm12
551+
csrrs t2, 0x25C, zero
552+
553+
# vstopi
554+
# name
555+
# CHECK-INST: csrrs t1, vstopi, zero
556+
# CHECK-ENC: encoding: [0x73,0x23,0x00,0xeb]
557+
# CHECK-INST-ALIAS: csrr t1, vstopi
558+
# uimm12
559+
# CHECK-INST: csrrs t2, vstopi, zero
560+
# CHECK-ENC: encoding: [0xf3,0x23,0x00,0xeb]
561+
# CHECK-INST-ALIAS: csrr t2, vstopi
562+
# name
563+
csrrs t1, vstopi, zero
564+
# uimm12
565+
csrrs t2, 0xEB0, zero

‎llvm/test/MC/RISCV/machine-csr-names.s

+88
Original file line numberDiff line numberDiff line change
@@ -2410,3 +2410,91 @@ csrrs t2, 0x30E, zero
24102410
csrrs t1, mstateen3, zero
24112411
# uimm12
24122412
csrrs t2, 0x30F, zero
2413+
2414+
#########################################
2415+
# Advanced Interrupt Architecture (Smaia and Ssaia)
2416+
#########################################
2417+
2418+
# miselect
2419+
# name
2420+
# CHECK-INST: csrrs t1, miselect, zero
2421+
# CHECK-ENC: encoding: [0x73,0x23,0x00,0x35]
2422+
# CHECK-INST-ALIAS: csrr t1, miselect
2423+
# uimm12
2424+
# CHECK-INST: csrrs t2, miselect, zero
2425+
# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x35]
2426+
# CHECK-INST-ALIAS: csrr t2, miselect
2427+
# name
2428+
csrrs t1, miselect, zero
2429+
# uimm12
2430+
csrrs t2, 0x350, zero
2431+
2432+
# mireg
2433+
# name
2434+
# CHECK-INST: csrrs t1, mireg, zero
2435+
# CHECK-ENC: encoding: [0x73,0x23,0x10,0x35]
2436+
# CHECK-INST-ALIAS: csrr t1, mireg
2437+
# uimm12
2438+
# CHECK-INST: csrrs t2, mireg, zero
2439+
# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x35]
2440+
# CHECK-INST-ALIAS: csrr t2, mireg
2441+
# name
2442+
csrrs t1, mireg, zero
2443+
# uimm12
2444+
csrrs t2, 0x351, zero
2445+
2446+
# mtopei
2447+
# name
2448+
# CHECK-INST: csrrs t1, mtopei, zero
2449+
# CHECK-ENC: encoding: [0x73,0x23,0xc0,0x35]
2450+
# CHECK-INST-ALIAS: csrr t1, mtopei
2451+
# uimm12
2452+
# CHECK-INST: csrrs t2, mtopei, zero
2453+
# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x35]
2454+
# CHECK-INST-ALIAS: csrr t2, mtopei
2455+
# name
2456+
csrrs t1, mtopei, zero
2457+
# uimm12
2458+
csrrs t2, 0x35C, zero
2459+
2460+
# mtopi
2461+
# name
2462+
# CHECK-INST: csrrs t1, mtopi, zero
2463+
# CHECK-ENC: encoding: [0x73,0x23,0x00,0xfb]
2464+
# CHECK-INST-ALIAS: csrr t1, mtopi
2465+
# uimm12
2466+
# CHECK-INST: csrrs t2, mtopi, zero
2467+
# CHECK-ENC: encoding: [0xf3,0x23,0x00,0xfb]
2468+
# CHECK-INST-ALIAS: csrr t2, mtopi
2469+
# name
2470+
csrrs t1, mtopi, zero
2471+
# uimm12
2472+
csrrs t2, 0xFB0, zero
2473+
2474+
# mvien
2475+
# name
2476+
# CHECK-INST: csrrs t1, mvien, zero
2477+
# CHECK-ENC: encoding: [0x73,0x23,0x80,0x30]
2478+
# CHECK-INST-ALIAS: csrr t1, mvien
2479+
# uimm12
2480+
# CHECK-INST: csrrs t2, mvien, zero
2481+
# CHECK-ENC: encoding: [0xf3,0x23,0x80,0x30]
2482+
# CHECK-INST-ALIAS: csrr t2, mvien
2483+
# name
2484+
csrrs t1, mvien, zero
2485+
# uimm12
2486+
csrrs t2, 0x308, zero
2487+
2488+
# mvip
2489+
# name
2490+
# CHECK-INST: csrrs t1, mvip, zero
2491+
# CHECK-ENC: encoding: [0x73,0x23,0x90,0x30]
2492+
# CHECK-INST-ALIAS: csrr t1, mvip
2493+
# uimm12
2494+
# CHECK-INST: csrrs t2, mvip, zero
2495+
# CHECK-ENC: encoding: [0xf3,0x23,0x90,0x30]
2496+
# CHECK-INST-ALIAS: csrr t2, mvip
2497+
# name
2498+
csrrs t1, mvip, zero
2499+
# uimm12
2500+
csrrs t2, 0x309, zero

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