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kazutakahiratakazutakahirata
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[Target] Use getConstantOperandVal (NFC)
1 parent fd35899 commit 7528cf5

9 files changed

+25
-42
lines changed

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 8 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2164,9 +2164,8 @@ void AArch64TargetLowering::computeKnownBitsForTargetNode(
21642164
break;
21652165
}
21662166
case AArch64ISD::MOVI: {
2167-
ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(0));
2168-
Known =
2169-
KnownBits::makeConstant(APInt(Known.getBitWidth(), CN->getZExtValue()));
2167+
Known = KnownBits::makeConstant(
2168+
APInt(Known.getBitWidth(), Op->getConstantOperandVal(0)));
21702169
break;
21712170
}
21722171
case AArch64ISD::LOADgot:
@@ -2183,8 +2182,8 @@ void AArch64TargetLowering::computeKnownBitsForTargetNode(
21832182
break;
21842183
}
21852184
case ISD::INTRINSIC_W_CHAIN: {
2186-
ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
2187-
Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
2185+
Intrinsic::ID IntID =
2186+
static_cast<Intrinsic::ID>(Op->getConstantOperandVal(1));
21882187
switch (IntID) {
21892188
default: return;
21902189
case Intrinsic::aarch64_ldaxr:
@@ -22284,8 +22283,8 @@ static SDValue performSETCCCombine(SDNode *N,
2228422283
isNullConstant(LHS->getOperand(0)) && isOneConstant(LHS->getOperand(1)) &&
2228522284
LHS->hasOneUse()) {
2228622285
// Invert CSEL's condition.
22287-
auto *OpCC = cast<ConstantSDNode>(LHS.getOperand(2));
22288-
auto OldCond = static_cast<AArch64CC::CondCode>(OpCC->getZExtValue());
22286+
auto OldCond =
22287+
static_cast<AArch64CC::CondCode>(LHS.getConstantOperandVal(2));
2228922288
auto NewCond = getInvertedCondCode(OldCond);
2229022289

2229122290
// csel 0, 1, !cond, X
@@ -24717,8 +24716,8 @@ void AArch64TargetLowering::ReplaceNodeResults(
2471724716
assert((VT == MVT::i8 || VT == MVT::i16) &&
2471824717
"custom lowering for unexpected type");
2471924718

24720-
ConstantSDNode *CN = cast<ConstantSDNode>(N->getOperand(0));
24721-
Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
24719+
Intrinsic::ID IntID =
24720+
static_cast<Intrinsic::ID>(N->getConstantOperandVal(0));
2472224721
switch (IntID) {
2472324722
default:
2472424723
return;

‎llvm/lib/Target/AMDGPU/R600ISelLowering.cpp

Lines changed: 4 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1619,17 +1619,15 @@ static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
16191619
for (unsigned i = 0; i < 4; i++) {
16201620
RemapSwizzle[i] = i;
16211621
if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1622-
unsigned Idx = cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1623-
->getZExtValue();
1622+
unsigned Idx = NewBldVec[i].getConstantOperandVal(1);
16241623
if (i == Idx)
16251624
isUnmovable[Idx] = true;
16261625
}
16271626
}
16281627

16291628
for (unsigned i = 0; i < 4; i++) {
16301629
if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1631-
unsigned Idx = cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1632-
->getZExtValue();
1630+
unsigned Idx = NewBldVec[i].getConstantOperandVal(1);
16331631
if (isUnmovable[Idx])
16341632
continue;
16351633
// Swap i and Idx
@@ -2002,9 +2000,7 @@ bool R600TargetLowering::FoldOperand(SDNode *ParentNode, unsigned SrcIdx,
20022000
if (RegisterSDNode *Reg =
20032001
dyn_cast<RegisterSDNode>(ParentNode->getOperand(OtherSrcIdx))) {
20042002
if (Reg->getReg() == R600::ALU_CONST) {
2005-
ConstantSDNode *Cst
2006-
= cast<ConstantSDNode>(ParentNode->getOperand(OtherSelIdx));
2007-
Consts.push_back(Cst->getZExtValue());
2003+
Consts.push_back(ParentNode->getConstantOperandVal(OtherSelIdx));
20082004
}
20092005
}
20102006
}
@@ -2044,8 +2040,7 @@ bool R600TargetLowering::FoldOperand(SDNode *ParentNode, unsigned SrcIdx,
20442040
ImmValue = FPC->getValueAPF().bitcastToAPInt().getZExtValue();
20452041
}
20462042
} else {
2047-
ConstantSDNode *C = cast<ConstantSDNode>(Src.getOperand(0));
2048-
uint64_t Value = C->getZExtValue();
2043+
uint64_t Value = Src.getConstantOperandVal(0);
20492044
if (Value == 0) {
20502045
ImmReg = R600::ZERO;
20512046
} else if (Value == 1) {

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 3 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -5742,8 +5742,7 @@ SDValue SITargetLowering::lowerIntrinsicLoad(MemSDNode *M, bool IsFormat,
57425742
static SDValue lowerICMPIntrinsic(const SITargetLowering &TLI,
57435743
SDNode *N, SelectionDAG &DAG) {
57445744
EVT VT = N->getValueType(0);
5745-
const auto *CD = cast<ConstantSDNode>(N->getOperand(3));
5746-
unsigned CondCode = CD->getZExtValue();
5745+
unsigned CondCode = N->getConstantOperandVal(3);
57475746
if (!ICmpInst::isIntPredicate(static_cast<ICmpInst::Predicate>(CondCode)))
57485747
return DAG.getUNDEF(VT);
57495748

@@ -5777,9 +5776,8 @@ static SDValue lowerICMPIntrinsic(const SITargetLowering &TLI,
57775776
static SDValue lowerFCMPIntrinsic(const SITargetLowering &TLI,
57785777
SDNode *N, SelectionDAG &DAG) {
57795778
EVT VT = N->getValueType(0);
5780-
const auto *CD = cast<ConstantSDNode>(N->getOperand(3));
57815779

5782-
unsigned CondCode = CD->getZExtValue();
5780+
unsigned CondCode = N->getConstantOperandVal(3);
57835781
if (!FCmpInst::isFPPredicate(static_cast<FCmpInst::Predicate>(CondCode)))
57845782
return DAG.getUNDEF(VT);
57855783

@@ -7419,9 +7417,7 @@ SDValue SITargetLowering::lowerImage(SDValue Op,
74197417
NumVDataDwords = Is64Bit ? 2 : 1;
74207418
}
74217419
} else {
7422-
auto *DMaskConst =
7423-
cast<ConstantSDNode>(Op.getOperand(ArgOffset + Intr->DMaskIndex));
7424-
DMask = DMaskConst->getZExtValue();
7420+
DMask = Op->getConstantOperandVal(ArgOffset + Intr->DMaskIndex);
74257421
DMaskLanes = BaseOpcode->Gather4 ? 4 : llvm::popcount(DMask);
74267422

74277423
if (BaseOpcode->Store) {

‎llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4246,8 +4246,7 @@ ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
42464246
static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
42474247
const ARMSubtarget *Subtarget) {
42484248
SDLoc dl(Op);
4249-
ConstantSDNode *SSIDNode = cast<ConstantSDNode>(Op.getOperand(2));
4250-
auto SSID = static_cast<SyncScope::ID>(SSIDNode->getZExtValue());
4249+
auto SSID = static_cast<SyncScope::ID>(Op.getConstantOperandVal(2));
42514250
if (SSID == SyncScope::SingleThread)
42524251
return Op;
42534252

@@ -4261,8 +4260,8 @@ static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
42614260
DAG.getConstant(0, dl, MVT::i32));
42624261
}
42634262

4264-
ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
4265-
AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
4263+
AtomicOrdering Ord =
4264+
static_cast<AtomicOrdering>(Op.getConstantOperandVal(1));
42664265
ARM_MB::MemBOpt Domain = ARM_MB::ISH;
42674266
if (Subtarget->isMClass()) {
42684267
// Only a full system barrier exists in the M-class architectures.
@@ -20087,8 +20086,8 @@ void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
2008720086
return;
2008820087
}
2008920088
case ISD::INTRINSIC_W_CHAIN: {
20090-
ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
20091-
Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
20089+
Intrinsic::ID IntID =
20090+
static_cast<Intrinsic::ID>(Op->getConstantOperandVal(1));
2009220091
switch (IntID) {
2009320092
default: return;
2009420093
case Intrinsic::arm_ldaex:

‎llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -701,8 +701,7 @@ void HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) {
701701
void HexagonDAGToDAGISel::SelectExtractSubvector(SDNode *N) {
702702
SDValue Inp = N->getOperand(0);
703703
MVT ResTy = N->getValueType(0).getSimpleVT();
704-
auto IdxN = cast<ConstantSDNode>(N->getOperand(1));
705-
unsigned Idx = IdxN->getZExtValue();
704+
unsigned Idx = N->getConstantOperandVal(1);
706705

707706
[[maybe_unused]] MVT InpTy = Inp.getValueType().getSimpleVT();
708707
[[maybe_unused]] unsigned ResLen = ResTy.getVectorNumElements();

‎llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2573,8 +2573,7 @@ SDValue HvxSelector::getVectorConstant(ArrayRef<uint8_t> Data,
25732573
void HvxSelector::selectExtractSubvector(SDNode *N) {
25742574
SDValue Inp = N->getOperand(0);
25752575
MVT ResTy = N->getValueType(0).getSimpleVT();
2576-
auto IdxN = cast<ConstantSDNode>(N->getOperand(1));
2577-
unsigned Idx = IdxN->getZExtValue();
2576+
unsigned Idx = N->getConstantOperandVal(1);
25782577

25792578
[[maybe_unused]] MVT InpTy = Inp.getValueType().getSimpleVT();
25802579
[[maybe_unused]] unsigned ResLen = ResTy.getVectorNumElements();

‎llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5262,9 +5262,7 @@ static SDValue PerformANDCombine(SDNode *N,
52625262
return SDValue();
52635263
}
52645264

5265-
unsigned ExtType =
5266-
cast<ConstantSDNode>(Val->getOperand(Val->getNumOperands()-1))->
5267-
getZExtValue();
5265+
unsigned ExtType = Val->getConstantOperandVal(Val->getNumOperands() - 1);
52685266
if (ExtType == ISD::SEXTLOAD) {
52695267
// If for some reason the load is a sextload, the and is needed to zero
52705268
// out the high 8 bits

‎llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6046,8 +6046,7 @@ SDValue SystemZTargetLowering::lowerIS_FPCLASS(SDValue Op,
60466046
SDLoc DL(Op);
60476047
MVT ResultVT = Op.getSimpleValueType();
60486048
SDValue Arg = Op.getOperand(0);
6049-
auto CNode = cast<ConstantSDNode>(Op.getOperand(1));
6050-
unsigned Check = CNode->getZExtValue();
6049+
unsigned Check = Op.getConstantOperandVal(1);
60516050

60526051
unsigned TDCMask = 0;
60536052
if (Check & fcSNan)

‎llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2355,8 +2355,7 @@ SDValue X86DAGToDAGISel::matchIndexRecursively(SDValue N,
23552355
Src.hasOneUse()) {
23562356
if (CurDAG->isBaseWithConstantOffset(Src)) {
23572357
SDValue AddSrc = Src.getOperand(0);
2358-
auto *AddVal = cast<ConstantSDNode>(Src.getOperand(1));
2359-
uint64_t Offset = (uint64_t)AddVal->getZExtValue();
2358+
uint64_t Offset = Src.getConstantOperandVal(1);
23602359
if (!foldOffsetIntoAddress(Offset * AM.Scale, AM)) {
23612360
SDLoc DL(N);
23622361
SDValue Res;

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