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[RISCV][GISel] Add simplest case of folding add with immediate into load/store address.
This covers the simm12 offset case.
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‎llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -307,6 +307,25 @@ RISCVInstructionSelector::selectAddrRegImm(MachineOperand &Root) const {
307307
}};
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}
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310+
if (isBaseWithConstantOffset(Root, MRI)) {
311+
MachineOperand &LHS = RootDef->getOperand(1);
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MachineOperand &RHS = RootDef->getOperand(2);
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MachineInstr *LHSDef = MRI.getVRegDef(LHS.getReg());
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MachineInstr *RHSDef = MRI.getVRegDef(RHS.getReg());
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int64_t RHSC = RHSDef->getOperand(1).getCImm()->getSExtValue();
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if (isInt<12>(RHSC)) {
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if (LHSDef->getOpcode() == TargetOpcode::G_FRAME_INDEX)
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return {{
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[=](MachineInstrBuilder &MIB) { MIB.add(LHSDef->getOperand(1)); },
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[=](MachineInstrBuilder &MIB) { MIB.addImm(RHSC); },
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}};
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324+
return {{[=](MachineInstrBuilder &MIB) { MIB.add(LHS); },
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[=](MachineInstrBuilder &MIB) { MIB.addImm(RHSC); }}};
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}
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}
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310329
// TODO: Need to get the immediate from a G_PTR_ADD. Should this be done in
311330
// the combiner?
312331
return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); },

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,11 @@
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%ptr0 = alloca i32
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ret void
1717
}
18+
define void @load_fi_gep_i32() {
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%ptr0 = alloca [2 x i32]
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ret void
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}
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define void @load_gep_i32(ptr %addr) { ret void }
1823
...
1924
---
2025
name: load_i8
@@ -213,3 +218,50 @@ body: |
213218
PseudoRET implicit $x10
214219
215220
...
221+
---
222+
name: load_fi_gep_i32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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stack:
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- { id: 0, name: ptr0, offset: 0, size: 8, alignment: 4 }
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body: |
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bb.0:
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; CHECK-LABEL: name: load_fi_gep_i32
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; CHECK: [[LW:%[0-9]+]]:gpr = LW %stack.0.ptr0, 4 :: (load (s32))
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; CHECK-NEXT: $x10 = COPY [[LW]]
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
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%1:gprb(s32) = G_CONSTANT i32 4
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%2:gprb(p0) = G_PTR_ADD %0(p0), %1(s32)
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%3:gprb(s32) = G_LOAD %2(p0) :: (load (s32))
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$x10 = COPY %3(s32)
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PseudoRET implicit $x10
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...
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---
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name: load_gep_i32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10
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; CHECK-LABEL: name: load_gep_i32
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; CHECK: liveins: $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
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; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32))
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; CHECK-NEXT: $x10 = COPY [[LW]]
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:gprb(p0) = COPY $x10
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%1:gprb(s32) = G_CONSTANT i32 4
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%2:gprb(p0) = G_PTR_ADD %0(p0), %1(s32)
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%3:gprb(s32) = G_LOAD %2(p0) :: (load (s32))
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$x10 = COPY %3(s32)
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PseudoRET implicit $x10
266+
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...

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,11 @@
2525
%ptr0 = alloca i64
2626
ret void
2727
}
28+
define void @load_fi_gep_i64_i64() {
29+
%ptr0 = alloca [2 x i64]
30+
ret void
31+
}
32+
define void @load_gep_i64_i64(ptr %addr) { ret void }
2833
...
2934
---
3035
name: load_i8_i64
@@ -478,3 +483,50 @@ body: |
478483
PseudoRET implicit $x10
479484
480485
...
486+
---
487+
name: load_fi_gep_i64_i64
488+
legalized: true
489+
regBankSelected: true
490+
tracksRegLiveness: true
491+
492+
stack:
493+
- { id: 0, name: ptr0, offset: 0, size: 16, alignment: 8 }
494+
495+
body: |
496+
bb.0:
497+
; CHECK-LABEL: name: load_fi_gep_i64_i64
498+
; CHECK: [[LD:%[0-9]+]]:gpr = LD %stack.0.ptr0, 8 :: (load (s64))
499+
; CHECK-NEXT: $x10 = COPY [[LD]]
500+
; CHECK-NEXT: PseudoRET implicit $x10
501+
%0:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
502+
%1:gprb(s64) = G_CONSTANT i64 8
503+
%2:gprb(p0) = G_PTR_ADD %0(p0), %1(s64)
504+
%3:gprb(s64) = G_LOAD %2(p0) :: (load (s64))
505+
$x10 = COPY %3(s64)
506+
PseudoRET implicit $x10
507+
508+
...
509+
---
510+
name: load_gep_i64_i64
511+
legalized: true
512+
regBankSelected: true
513+
tracksRegLiveness: true
514+
body: |
515+
bb.0:
516+
liveins: $x10
517+
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; CHECK-LABEL: name: load_gep_i64_i64
519+
; CHECK: liveins: $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
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; CHECK-NEXT: [[LD:%[0-9]+]]:gpr = LD [[COPY]], 8 :: (load (s64))
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; CHECK-NEXT: $x10 = COPY [[LD]]
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:gprb(p0) = COPY $x10
526+
%1:gprb(s64) = G_CONSTANT i64 8
527+
%2:gprb(p0) = G_PTR_ADD %0(p0), %1(s64)
528+
%3:gprb(s64) = G_LOAD %2(p0) :: (load (s64))
529+
$x10 = COPY %3(s64)
530+
PseudoRET implicit $x10
531+
532+
...

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv32.mir

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,11 @@
1111
%ptr0 = alloca i32
1212
ret void
1313
}
14+
define void @store_fi_gep_i32(ptr %val) {
15+
%ptr0 = alloca [2 x i32]
16+
ret void
17+
}
18+
define void @store_gep_i32(i32 %val, ptr %addr) { ret void }
1419
...
1520
---
1621
name: store_i8
@@ -125,3 +130,54 @@ body: |
125130
PseudoRET
126131
127132
...
133+
---
134+
name: store_fi_gep_i32
135+
legalized: true
136+
regBankSelected: true
137+
tracksRegLiveness: true
138+
139+
stack:
140+
- { id: 0, name: ptr0, offset: 0, size: 8, alignment: 4 }
141+
142+
body: |
143+
bb.0:
144+
liveins: $x10
145+
146+
; CHECK-LABEL: name: store_fi_gep_i32
147+
; CHECK: liveins: $x10
148+
; CHECK-NEXT: {{ $}}
149+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
150+
; CHECK-NEXT: SW [[COPY]], %stack.0.ptr0, 4 :: (store (s32))
151+
; CHECK-NEXT: PseudoRET
152+
%0:gprb(s32) = COPY $x10
153+
%1:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
154+
%2:gprb(s32) = G_CONSTANT i32 4
155+
%3:gprb(p0) = G_PTR_ADD %1(p0), %2(s32)
156+
G_STORE %0(s32), %3(p0) :: (store (s32))
157+
PseudoRET
158+
159+
...
160+
---
161+
name: store_gep_i32
162+
legalized: true
163+
regBankSelected: true
164+
tracksRegLiveness: true
165+
body: |
166+
bb.0:
167+
liveins: $x10, $x11
168+
169+
; CHECK-LABEL: name: store_gep_i32
170+
; CHECK: liveins: $x10, $x11
171+
; CHECK-NEXT: {{ $}}
172+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
173+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
174+
; CHECK-NEXT: SW [[COPY]], [[COPY1]], 4 :: (store (s32))
175+
; CHECK-NEXT: PseudoRET
176+
%0:gprb(s32) = COPY $x10
177+
%1:gprb(p0) = COPY $x11
178+
%2:gprb(s32) = G_CONSTANT i32 4
179+
%3:gprb(p0) = G_PTR_ADD %1(p0), %2(s32)
180+
G_STORE %0(s32), %3(p0) :: (store (s32))
181+
PseudoRET
182+
183+
...

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv64.mir

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,11 @@
1515
%ptr0 = alloca i64
1616
ret void
1717
}
18+
define void @store_fi_gep_i64_i64(ptr %val) {
19+
%ptr0 = alloca [2 x i64]
20+
ret void
21+
}
22+
define void @store_gep_i64_i64(i32 %val, ptr %addr) { ret void }
1823
...
1924
---
2025
name: store_i8_i64
@@ -247,3 +252,54 @@ body: |
247252
PseudoRET
248253
249254
...
255+
---
256+
name: store_fi_gep_i64_i64
257+
legalized: true
258+
regBankSelected: true
259+
tracksRegLiveness: true
260+
261+
stack:
262+
- { id: 0, name: ptr0, offset: 0, size: 16, alignment: 8 }
263+
264+
body: |
265+
bb.0:
266+
liveins: $x10
267+
268+
; CHECK-LABEL: name: store_fi_gep_i64_i64
269+
; CHECK: liveins: $x10
270+
; CHECK-NEXT: {{ $}}
271+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
272+
; CHECK-NEXT: SD [[COPY]], %stack.0.ptr0, 8 :: (store (s64))
273+
; CHECK-NEXT: PseudoRET
274+
%0:gprb(s64) = COPY $x10
275+
%1:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
276+
%2:gprb(s64) = G_CONSTANT i64 8
277+
%3:gprb(p0) = G_PTR_ADD %1(p0), %2(s64)
278+
G_STORE %0(s64), %3(p0) :: (store (s64))
279+
PseudoRET
280+
281+
...
282+
---
283+
name: store_gep_i64_i64
284+
legalized: true
285+
regBankSelected: true
286+
tracksRegLiveness: true
287+
body: |
288+
bb.0:
289+
liveins: $x10, $x11
290+
291+
; CHECK-LABEL: name: store_gep_i64_i64
292+
; CHECK: liveins: $x10, $x11
293+
; CHECK-NEXT: {{ $}}
294+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
295+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
296+
; CHECK-NEXT: SD [[COPY]], [[COPY1]], 8 :: (store (s64))
297+
; CHECK-NEXT: PseudoRET
298+
%0:gprb(s64) = COPY $x10
299+
%1:gprb(p0) = COPY $x11
300+
%2:gprb(s64) = G_CONSTANT i64 8
301+
%3:gprb(p0) = G_PTR_ADD %1(p0), %2(s64)
302+
G_STORE %0(s64), %3(p0) :: (store (s64))
303+
PseudoRET
304+
305+
...

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