[DAG] combineShiftToAVG - ensure the reduced demanded value type is smaller than the original.

Now we have promotion support we should be able to remove the next-power-of-2 code entirely, but this is good enough for now.

Author: RKSimon

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

@@ -1060,6 +1060,8 @@ static SDValue combineShiftToAVG(SDValue Op,
   unsigned MinWidth =
       std::max<unsigned>(VT.getScalarSizeInBits() - KnownBits, 8);
   EVT NVT = EVT::getIntegerVT(*DAG.getContext(), llvm::bit_ceil(MinWidth));
+  if (NVT.getScalarSizeInBits() > VT.getScalarSizeInBits())
+    return SDValue();
   if (VT.isVector())
     NVT = EVT::getVectorVT(*DAG.getContext(), NVT, VT.getVectorElementCount());
   if (TLO.LegalOperations() && !TLI.isOperationLegal(AVGOpc, NVT)) {

llvm/test/CodeGen/AArch64/arm64-vhadd.ll

@@ -1395,10 +1395,8 @@ define <8 x i8> @sextmask3v8i8(<8 x i16> %src1, <8 x i8> %src2) {
 define <4 x i16> @ext_via_i19(<4 x i16> %a) {
 ; CHECK-LABEL: ext_via_i19:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    movi.4s v1, #1
-; CHECK-NEXT:    uaddw.4s v0, v1, v0
-; CHECK-NEXT:    uhadd.4s v0, v0, v1
-; CHECK-NEXT:    xtn.4h v0, v0
+; CHECK-NEXT:    movi.4h v1, #1
+; CHECK-NEXT:    urhadd.4h v0, v0, v1
 ; CHECK-NEXT:    ret
   %t3 = zext <4 x i16> %a to <4 x i32>
   %t4 = add <4 x i32> %t3, <i32 1, i32 1, i32 1, i32 1>